cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal ram : RAM_TYPE := (  0 => "11101011000000000000000000010111", -- call +1
  16
  17                                     1 => "11101101000010000000000000111000", -- r1 = 7
  18                                     2 => "11101101000100000000000000101000", -- r2 = 5
  19                                     3 => "11101101000110000000000000100000", -- r3 = 4
  20                                     4 => "11100000001000010001100000000000", -- r4 = r2 + r3
  21                                     5 => "11100010001010100000100000000000", -- r5 = r4 and r1
  22
  23                                     6 => "11101011000000000000000000001011", -- r0 = r0 + 1
  24 --                                  7 => "11101100100000000000000000011000", -- cmpi r0 , 2
  25
  26                                     7 => "00001011011111111111110010000111", -- jump -7
  27                                     8 => "11101011000000000000000010000010", -- jump +1
  28                                    --10 => "11101011000000000000000010000010", -- jump +1
  29
  30                                    9 => "11100111101010100000000000000001", -- stw r5,r4,1
  31                                    10 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
  32
  33                                    11 => "11101011000000000000000000000010", -- jump +0
  34
  35
  36
  37
  38                                   others => x"F0000000");
  39
  40 --      signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
  41 --
  42 --                                  1 => "11101101000010000000000000111000", -- r1 = 7
  43 --                                  2 => "11101101000100000000000000101000", -- r2 = 5
  44 --                                  3 => "11101101000110000000000000100000", -- r3 = 4
  45 --                                  4 => "11100000001000010001100000000000", -- r4 = r2 + r3
  46 --                                  5 => "11100010001010100000100000000000", -- r5 = r4 and r1
  47 --
  48 --                                  6 => "11100001000000000000000000001000", -- r0 = r0 + 1
  49 --                                  7 => "11101100100000000000000000011000", -- cmpi r0 , 2
  50 --
  51 --                                  8 => "00001011011111111111110010000111", -- jump -7
  52 --                                  9 => "11101011000000000000000010000010", -- jump +1
  53 --                                 --10 => "11101011000000000000000010000010", -- jump +1
  54 --
  55   --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
  56         --                         11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
  57 --
  58 --                                 12 => "11101011000000000000000000000010", -- jump +0
  59
  60
  61
  62
  63 --                                others => x"F0000000");
  64
  65 --      signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  66 --                                  1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  67 --                                  2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  68 --                                  3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  69 --                                  4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  70 --                                  5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  71 --                                  6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
  72 --                                  7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
  73 --                                  8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
  74 --                                  9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
  75 --                                 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
  76 --                                 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
  77 --                                 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
  78 --                                 13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
  79 --                                 14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
  80 --                                 15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
  81 --                                 16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
  82 --                                 17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
  83 --                                 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
  84 --                                 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
  85 --                                others => x"F0000000");
  86
  87
  88 begin
  89         process(clk)
  90         begin
  91                 if rising_edge(clk) then
  92                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
  93
  94                         if wr_en = '1' then
  95                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  96                         end if;
  97                 end if;
  98         end process;
  99 end architecture behaviour;