cpu/src/r2_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r2_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13         signal ram : RAM_TYPE := (
  14                                 0 => x"00000000",
  15                                 1 => x"00000000",
  16                                 2 => x"00000000",
  17                                 3 => x"00000000",
  18                                 others=> (others => '0'));
  19
  20 begin
  21         process(clk)
  22         begin
  23                 if rising_edge(clk) then
  24                         data_out1 <= ram(to_integer(UNSIGNED(rd_addr1)));
  25                         data_out2 <= ram(to_integer(UNSIGNED(rd_addr2)));
  26
  27                         if wr_en = '1' then
  28                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  29                         end if;
  30                 end if;
  31         end process;
  32 end architecture behaviour;