cpu/src/r2_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 architecture behaviour of r2_w_ram is
   7
   8         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
   9         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  10
  11         signal ram : RAM_TYPE; --:= (others=> x"00");
  12
  13 begin
  14         process(clk)
  15         begin
  16                 if rising_edge(clk) then
  17                         data_out1 <= ram(to_integer(UNSIGNED(rd_addr1)));
  18                         data_out2 <= ram(to_integer(UNSIGNED(rd_addr2)));
  19
  20                         if wr_en = '1' then
  21                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  22                         end if;
  23                 end if;
  24         end process;
  25 end architecture behaviour;