2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
8 -------------------------------------------------------------------------------
10 -------------------------------------------------------------------------------
16 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 architecture behavior of pipeline_tb is
21 constant cc : time := 30 ns; -- test clock period
23 signal sys_clk_pin : std_logic;
24 signal sys_res_n_pin : std_logic;
27 signal dummy : std_logic;
29 signal jump_result_pin : instruction_addr_t;
30 signal prediction_result_pin : instruction_addr_t;
31 signal branch_prediction_bit_pin : std_logic;
32 signal alu_jump_bit_pin : std_logic;
33 signal instruction_pin : instruction_word_t;
34 signal prog_cnt : instruction_addr_t;
36 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
37 signal reg_wr_data_pin : gp_register_t;
38 signal reg_we_pin : std_logic;
39 signal to_next_stage_pin : dec_op;
41 signal result_pin : gp_register_t;--reg
42 signal result_addr_pin : gp_addr_t;--reg
43 signal addr_pin : word_t; --memaddr
44 signal data_pin : gp_register_t; --mem data --ureg
45 signal alu_jump_pin : std_logic;--reg
46 signal brpr_pin : std_logic; --reg
47 signal wr_en_pin : std_logic;--regop --reg
48 signal dmem_pin : std_logic;--memop
49 signal dmem_wr_en_pin : std_logic;
50 signal hword_pin : std_logic;
51 signal byte_s_pin : std_logic;
52 signal nop_pin : std_logic;
57 -- instruction_ram : r_w_ram
59 -- PHYS_INSTR_ADDR_WIDTH,
65 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
66 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
72 fetch_st : fetch_stage
81 clk => sys_clk_pin, --: in std_logic;
82 reset => sys_res_n_pin, --: in std_logic;
85 jump_result => jump_result_pin, --: in instruction_addr_t;
86 prediction_result => prediction_result_pin, --: in instruction_addr_t;
87 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
88 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
91 instruction => instruction_pin, --: out instruction_word_t
95 decode_st : decode_stage
105 clk => sys_clk_pin, --: in std_logic;
106 reset => sys_res_n_pin, -- : in std_logic;
109 instruction => instruction_pin, --: in instruction_word_t;
110 prog_cnt => prog_cnt,
111 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
112 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
113 reg_we => reg_we_pin, --: in std_logic;
117 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
118 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
119 to_next_stage => to_next_stage_pin
122 exec_st : execute_stage
124 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
125 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
127 writeback_st : writeback_stage
128 generic map('0', '1')
129 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
130 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
131 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
136 nop_pin <= (alu_jump_bit_pin xor brpr_pin);
138 -------------------------------------------------------------------------------
139 -- generate simulation clock
140 -------------------------------------------------------------------------------
149 -------------------------------------------------------------------------------
151 -------------------------------------------------------------------------------
154 -- wait for n clock cycles
155 procedure icwait(cycles : natural) is
157 for i in 1 to cycles loop
158 wait until sys_clk_pin = '1' and sys_clk_pin'event;
163 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
166 sys_res_n_pin <= '0';
167 -- reg_w_addr_pin <= (others => '0');
168 -- reg_wr_data_pin <= (others => '0');
169 -- reg_we_pin <= '0';
173 sys_res_n_pin <= '1';
174 wait until sys_res_n_pin = '1';
179 ---------------------------------------------------------------------------
181 ---------------------------------------------------------------------------
183 report "Test finished"
191 -------------------------------------------------------------------------------
193 -------------------------------------------------------------------------------
194 configuration pipeline_conf_beh of pipeline_tb is
196 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
198 for decode_st : decode_stage use entity work.decode_stage(behav);
200 for exec_st : execute_stage use entity work.execute_stage(behav);
202 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
206 end pipeline_conf_beh;