2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 -------------------------------------------------------------------------------
9 -------------------------------------------------------------------------------
15 -------------------------------------------------------------------------------
17 -------------------------------------------------------------------------------
18 architecture behavior of pipeline_tb is
20 constant cc : time := 30 ns; -- test clock period
22 signal sys_clk_pin : std_logic;
23 signal sys_res_n_pin : std_logic;
26 signal dummy : std_logic;
28 signal jump_result_pin : instruction_addr_t;
29 signal prediction_result_pin : instruction_addr_t;
30 signal branch_prediction_bit_pin : std_logic;
31 signal alu_jump_bit_pin : std_logic;
32 signal instruction_pin : instruction_word_t;
34 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
35 signal reg_wr_data_pin : gp_register_t;
36 signal reg_we_pin : std_logic;
37 signal to_next_stage_pin : dec_op;
39 signal result_pin : gp_register_t;--reg
40 signal result_addr_pin : gp_addr_t;--reg
41 signal addr_pin : word_t; --memaddr
42 signal data_pin : gp_register_t; --mem data --ureg
43 signal alu_jump_pin : std_logic;--reg
44 signal brpr_pin : std_logic; --reg
45 signal wr_en_pin : std_logic;--regop --reg
46 signal dmem_pin : std_logic;--memop
47 signal dmem_wr_en_pin : std_logic;
48 signal hword_pin : std_logic;
49 signal byte_s_pin : std_logic;
50 signal nop_pin : std_logic;
54 -- instruction_ram : r_w_ram
56 -- PHYS_INSTR_ADDR_WIDTH,
62 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
63 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
69 fetch_st : fetch_stage
78 clk => sys_clk_pin, --: in std_logic;
79 reset => sys_res_n_pin, --: in std_logic;
82 jump_result => jump_result_pin, --: in instruction_addr_t;
83 prediction_result => prediction_result_pin, --: in instruction_addr_t;
84 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
85 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
88 instruction => instruction_pin --: out instruction_word_t
91 decode_st : decode_stage
101 clk => sys_clk_pin, --: in std_logic;
102 reset => sys_res_n_pin, -- : in std_logic;
105 instruction => instruction_pin, --: in instruction_word_t;
106 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
107 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
108 reg_we => reg_we_pin, --: in std_logic;
112 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
113 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
114 to_next_stage => to_next_stage_pin
117 exec_st : execute_stage
119 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
120 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
122 writeback_st : writeback_stage
123 generic map('0', '1')
124 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
125 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
126 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
129 nop_pin <= (alu_jump_bit_pin xor brpr_pin);
131 -------------------------------------------------------------------------------
132 -- generate simulation clock
133 -------------------------------------------------------------------------------
142 -------------------------------------------------------------------------------
144 -------------------------------------------------------------------------------
147 -- wait for n clock cycles
148 procedure icwait(cycles : natural) is
150 for i in 1 to cycles loop
151 wait until sys_clk_pin = '1' and sys_clk_pin'event;
156 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 sys_res_n_pin <= '0';
160 -- reg_w_addr_pin <= (others => '0');
161 -- reg_wr_data_pin <= (others => '0');
162 -- reg_we_pin <= '0';
166 sys_res_n_pin <= '1';
167 wait until sys_res_n_pin = '1';
172 ---------------------------------------------------------------------------
174 ---------------------------------------------------------------------------
176 report "Test finished"
184 -------------------------------------------------------------------------------
186 -------------------------------------------------------------------------------
187 configuration pipeline_conf_beh of pipeline_tb is
189 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
191 for decode_st : decode_stage use entity work.decode_stage(behav);
193 for exec_st : execute_stage use entity work.execute_stage(behav);
195 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
199 end pipeline_conf_beh;