cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34                 signal prog_cnt : instruction_addr_t;
  35
  36                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  37                 signal reg_wr_data_pin : gp_register_t;
  38                 signal reg_we_pin : std_logic;
  39                 signal to_next_stage_pin : dec_op;
  40
  41                  signal result_pin : gp_register_t;--reg
  42                  signal result_addr_pin : gp_addr_t;--reg
  43                  signal addr_pin : word_t; --memaddr
  44                  signal data_pin : gp_register_t; --mem data --ureg
  45                  signal alu_jump_pin : std_logic;--reg
  46                  signal brpr_pin  : std_logic;  --reg
  47                  signal wr_en_pin : std_logic;--regop --reg
  48                  signal dmem_pin  : std_logic;--memop
  49                  signal dmem_wr_en_pin : std_logic;
  50                  signal hword_pin  : std_logic;
  51                  signal byte_s_pin : std_logic;
  52                  signal nop_pin : std_logic;
  53
  54
  55 begin
  56
  57 --              instruction_ram : r_w_ram
  58 --              generic map (
  59 --                      PHYS_INSTR_ADDR_WIDTH,
  60 --                      WORD_WIDTH
  61 --              )
  62 --
  63 --              port map (
  64 --                      sys_clk,
  65 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  66 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  67 --                      instr_we,
  68 --                      instr_wr_data,
  69 --                      instr_rd_data
  70 --              );
  71
  72         fetch_st : fetch_stage
  73                 generic map (
  74
  75                         '0',
  76                         '1'
  77                 )
  78
  79                 port map (
  80                 --System inputs
  81                         clk => sys_clk_pin, --: in std_logic;
  82                         reset => sys_res_n_pin, --: in std_logic;
  83
  84                 --Data inputs
  85                         jump_result => jump_result_pin, --: in instruction_addr_t;
  86                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  87                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  88                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  89
  90                 --Data outputs
  91                         instruction => instruction_pin, --: out instruction_word_t
  92                         prog_cnt => prog_cnt
  93                 );
  94
  95         decode_st : decode_stage
  96                 generic map (
  97                         -- active reset value
  98                         '0',
  99                         -- active logic value
 100                         '1'
 101
 102                         )
 103                 port map (
 104                 --System inputs
 105                         clk => sys_clk_pin, --: in std_logic;
 106                         reset => sys_res_n_pin, -- : in std_logic;
 107
 108                 --Data inputs
 109                         instruction => instruction_pin, --: in instruction_word_t;
 110                         prog_cnt => prog_cnt,
 111                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 112                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 113                         reg_we => reg_we_pin, --: in std_logic;
 114                         nop => nop_pin,
 115
 116                 --Data outputs
 117                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 118                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 119                         to_next_stage => to_next_stage_pin
 120
 121                 );
 122           exec_st : execute_stage
 123                 generic map('0')
 124                 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
 125                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 126
 127           writeback_st : writeback_stage
 128                 generic map('0', '1')
 129                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 130                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 131                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 132
 133
 134
 135
 136         nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
 137
 138 -------------------------------------------------------------------------------
 139 -- generate simulation clock
 140 -------------------------------------------------------------------------------
 141   CLKGEN : process
 142   begin
 143     sys_clk_pin <= '1';
 144     wait for cc/2;
 145     sys_clk_pin <= '0';
 146     wait for cc/2;
 147   end process CLKGEN;
 148
 149 -------------------------------------------------------------------------------
 150 -- test the design
 151 -------------------------------------------------------------------------------
 152   TEST_IT : process
 153
 154     -- wait for n clock cycles
 155     procedure icwait(cycles : natural) is
 156     begin
 157       for i in 1 to cycles loop
 158         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 159       end loop;
 160     end;
 161
 162   begin
 163     -----------------------------------------------------------------------------
 164     -- initial reset
 165     -----------------------------------------------------------------------------
 166         sys_res_n_pin <= '0';
 167 --      reg_w_addr_pin <= (others => '0');
 168 --      reg_wr_data_pin <= (others => '0');
 169 --      reg_we_pin <= '0';
 170
 171         icwait(10);
 172         dummy <= '1';
 173         sys_res_n_pin <= '1';
 174         wait until sys_res_n_pin = '1';
 175
 176
 177         icwait(100000);
 178
 179     ---------------------------------------------------------------------------
 180     -- exit testbench
 181     ---------------------------------------------------------------------------
 182     assert false
 183       report "Test finished"
 184       severity error;
 185
 186   end process test_it;
 187
 188 end behavior;
 189
 190
 191 -------------------------------------------------------------------------------
 192 -- configuration
 193 -------------------------------------------------------------------------------
 194 configuration pipeline_conf_beh of pipeline_tb is
 195   for behavior
 196     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 197     end for;
 198     for decode_st : decode_stage use entity work.decode_stage(behav);
 199     end for;
 200     for exec_st : execute_stage use entity work.execute_stage(behav);
 201     end for;
 202     for writeback_st : writeback_stage use entity work.writeback_stage(behav);
 203     end for;
 204
 205   end for;
 206 end pipeline_conf_beh;