1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
27 use work.core_pkg.all;
28 use work.extension_pkg.all;
29 -------------------------------------------------------------------------------
31 -------------------------------------------------------------------------------
37 -------------------------------------------------------------------------------
39 -------------------------------------------------------------------------------
40 architecture behavior of pipeline_tb is
42 constant cc : time := 20 ns; -- test clock period
43 constant SYS_CLOCK_FREQ : integer := 50000000;
44 constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
46 signal sys_clk_pin : std_logic;
47 signal sys_res_n_pin : std_logic;
50 signal dummy : std_logic;
52 signal jump_result_pin : instruction_addr_t;
53 signal prediction_result_pin : instruction_addr_t;
54 signal branch_prediction_bit_pin : std_logic;
55 signal alu_jump_bit_pin : std_logic;
56 signal instruction_pin : instruction_word_t;
57 signal prog_cnt : instruction_addr_t;
59 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
60 signal reg_wr_data_pin : gp_register_t;
61 signal reg_we_pin : std_logic;
62 signal to_next_stage_pin : dec_op;
64 signal result_pin : gp_register_t;--reg
65 signal result_addr_pin : gp_addr_t;--reg
66 signal addr_pin : word_t; --memaddr
67 signal data_pin : gp_register_t; --mem data --ureg
68 signal alu_jump_pin : std_logic;--reg
69 signal brpr_pin : std_logic; --reg
70 signal wr_en_pin : std_logic;--regop --reg
71 signal dmem_pin : std_logic;--memop
72 signal dmem_wr_en_pin : std_logic;
73 signal hword_pin : std_logic;
74 signal byte_s_pin, tx_pin, rx_pin : std_logic;
76 signal gpm_in_pin : extmod_rec;
77 signal gpm_out_pin : gp_register_t;
78 signal nop_pin : std_logic;
80 signal cycle_cnt : integer;
82 signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
83 signal int_req_pin : interrupt_t;
85 signal new_im_data :std_logic;
86 signal im_addr, im_data : gp_register_t;
90 -- instruction_ram : r_w_ram
92 -- PHYS_INSTR_ADDR_WIDTH,
98 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
99 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
105 fetch_st : fetch_stage
114 clk => sys_clk_pin, --: in std_logic;
115 reset => sys_res_n_pin, --: in std_logic;
118 jump_result => jump_result_pin, --: in instruction_addr_t;
119 prediction_result => prediction_result_pin, --: in instruction_addr_t;
120 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
121 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
122 new_im_data_in => new_im_data,
127 instruction => instruction_pin, --: out instruction_word_t
128 prog_cnt => prog_cnt,
129 int_req => int_req_pin
132 decode_st : decode_stage
134 -- active reset value
136 -- active logic value
142 clk => sys_clk_pin, --: in std_logic;
143 reset => sys_res_n_pin, -- : in std_logic;
146 instruction => instruction_pin, --: in instruction_word_t;
147 prog_cnt => prog_cnt,
148 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
149 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
150 reg_we => reg_we_pin, --: in std_logic;
154 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
155 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
156 to_next_stage => to_next_stage_pin
159 exec_st : execute_stage
161 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
162 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
164 writeback_st : writeback_stage
165 generic map('0', '1', "altera",50)
166 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
167 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
168 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
173 nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
175 -------------------------------------------------------------------------------
176 -- generate simulation clock
177 -------------------------------------------------------------------------------
187 cnt : process(sys_clk_pin, sys_res_n_pin)
191 if (sys_res_n_pin = '0') then
193 elsif (sys_clk_pin'event and sys_clk_pin = '1') then
194 cycle_cnt <= cycle_cnt + 1;
198 -------------------------------------------------------------------------------
200 -------------------------------------------------------------------------------
203 -- wait for n clock cycles
204 procedure icwait(cycles : natural) is
206 for i in 1 to cycles loop
207 wait until sys_clk_pin = '1' and sys_clk_pin'event;
211 procedure txd(trans_data : in std_logic_vector) is
214 rx_pin <= trans_data(i);
215 report "bit: " & std_logic'image(trans_data(i));
218 -- icwait(BAUD_COUNT);
225 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
228 sys_res_n_pin <= '0';
230 -- reg_w_addr_pin <= (others => '0');
231 -- reg_wr_data_pin <= (others => '0');
232 -- reg_we_pin <= '0';
236 sys_res_n_pin <= '1';
237 wait until sys_res_n_pin = '1';
248 ---------------------------------------------------------------------------
250 ---------------------------------------------------------------------------
252 report "Test finished"
260 -------------------------------------------------------------------------------
262 -------------------------------------------------------------------------------
263 configuration pipeline_conf_beh of pipeline_tb is
265 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
267 for decode_st : decode_stage use entity work.decode_stage(behav);
269 for exec_st : execute_stage use entity work.execute_stage(behav);
271 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
275 end pipeline_conf_beh;