cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34
  35                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  36                 signal reg_wr_data_pin : gp_register_t;
  37                 signal reg_we_pin : std_logic;
  38                 signal reg1_rd_data_pin : gp_register_t;
  39                 signal reg2_rd_data_pin : gp_register_t;
  40
  41
  42 begin
  43
  44 --              instruction_ram : r_w_ram
  45 --              generic map (
  46 --                      PHYS_INSTR_ADDR_WIDTH,
  47 --                      WORD_WIDTH
  48 --              )
  49 --
  50 --              port map (
  51 --                      sys_clk,
  52 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  53 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  54 --                      instr_we,
  55 --                      instr_wr_data,
  56 --                      instr_rd_data
  57 --              );
  58
  59         fetch_st : fetch_stage
  60                 generic map (
  61
  62                         '0',
  63                         '1'
  64                 )
  65
  66                 port map (
  67                 --System inputs
  68                         clk => sys_clk_pin, --: in std_logic;
  69                         reset => sys_res_n_pin, --: in std_logic;
  70
  71                 --Data inputs
  72                         jump_result => jump_result_pin, --: in instruction_addr_t;
  73                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  74                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  75                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  76
  77                 --Data outputs
  78                         instruction => instruction_pin --: out instruction_word_t
  79                 );
  80
  81         decode_st : decode_stage
  82                 generic map (
  83                         -- active reset value
  84                         '0',
  85                         -- active logic value
  86                         '1'
  87
  88                         )
  89                 port map (
  90                 --System inputs
  91                         clk => sys_clk_pin, --: in std_logic;
  92                         reset => sys_res_n_pin, -- : in std_logic;
  93
  94                 --Data inputs
  95                         instruction => instruction_pin, --: in instruction_word_t;
  96                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  97                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
  98                         reg_we => reg_we_pin, --: in std_logic;
  99
 100                 --Data outputs
 101                         reg1_rd_data => reg1_rd_data_pin, --: gp_register_t;
 102                         reg2_rd_data => reg2_rd_data_pin, --: gp_register_t;
 103                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 104                         branch_prediction_bit => branch_prediction_bit_pin --: std_logic
 105
 106                 );
 107
 108
 109
 110 -------------------------------------------------------------------------------
 111 -- generate simulation clock
 112 -------------------------------------------------------------------------------
 113   CLKGEN : process
 114   begin
 115     sys_clk_pin <= '1';
 116     wait for cc/2;
 117     sys_clk_pin <= '0';
 118     wait for cc/2;
 119   end process CLKGEN;
 120
 121 -------------------------------------------------------------------------------
 122 -- test the design
 123 -------------------------------------------------------------------------------
 124   TEST_IT : process
 125
 126     -- wait for n clock cycles
 127     procedure icwait(cycles : natural) is
 128     begin
 129       for i in 1 to cycles loop
 130         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 131       end loop;
 132     end;
 133
 134   begin
 135     -----------------------------------------------------------------------------
 136     -- initial reset
 137     -----------------------------------------------------------------------------
 138         sys_res_n_pin <= '0';
 139         reg_w_addr_pin <= (others => '0');
 140         reg_wr_data_pin <= (others => '0');
 141         reg_we_pin <= '0';
 142
 143         icwait(10);
 144         dummy <= '1';
 145         sys_res_n_pin <= '1';
 146         wait until sys_res_n_pin = '1';
 147
 148
 149         icwait(100000);
 150
 151     ---------------------------------------------------------------------------
 152     -- exit testbench
 153     ---------------------------------------------------------------------------
 154     assert false
 155       report "Test finished"
 156       severity error;
 157
 158   end process test_it;
 159
 160 end behavior;
 161
 162
 163 -------------------------------------------------------------------------------
 164 -- configuration
 165 -------------------------------------------------------------------------------
 166 configuration pipeline_conf_beh of pipeline_tb is
 167   for behavior
 168     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 169     end for;
 170     for decode_st : decode_stage use entity work.decode_stage(behav);
 171     end for;
 172
 173   end for;
 174 end pipeline_conf_beh;