cpu/src/fetch_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7
   8 architecture behav of fetch_stage is
   9
  10 signal instr_w_addr      : instruction_addr_t;
  11 signal instr_r_addr      : instruction_addr_t;
  12 signal instr_r_addr_nxt  : instruction_addr_t;
  13 signal instr_we          : std_logic;
  14 signal instr_wr_data     : instruction_word_t;
  15 signal instr_rd_data     : instruction_word_t;
  16
  17 begin
  18
  19         instruction_ram : r_w_ram
  20                 generic map (
  21                         PHYS_INSTR_ADDR_WIDTH,
  22                         WORD_WIDTH
  23                 )
  24
  25                 port map (
  26                         sys_clk,
  27                         instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  28                         instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  29                         instr_we,
  30                         instr_wr_data,
  31                         instr_rd_data
  32                 );
  33
  34 syn: process(sys_clk, reset)
  35
  36 begin
  37
  38         if (reset = RESET_VALUE) then
  39                 instr_r_addr <= (others => '0');
  40         elsif rising_edge(sys_clk) then
  41                 instr_r_addr <= instr_r_addr_nxt;
  42         end if;
  43
  44 end process;
  45
  46
  47 asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit)
  48
  49 begin
  50
  51         instruction <= instr_rd_data;
  52         instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
  53
  54         if (alu_jump_bit = LOGIC_ACT) then
  55                 instr_r_addr_nxt <= jump_result;
  56         elsif (branch_prediction_bit = LOGIC_ACT) then
  57                 instr_r_addr_nxt <= prediction_result;
  58         end if;
  59
  60 end process;
  61
  62 end behav;
  63