cpu/src/fetch_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7 use work.mem_pkg.all;
   8
   9 architecture behav of fetch_stage is
  10
  11 signal instr_w_addr      : instruction_addr_t;
  12 signal instr_r_addr      : instruction_addr_t;
  13 signal instr_r_addr_nxt  : instruction_addr_t;
  14 signal instr_we          : std_logic;
  15 signal instr_wr_data     : instruction_word_t;
  16 signal instr_rd_data     : instruction_word_t;
  17
  18 begin
  19
  20         instruction_ram : r_w_ram
  21                 generic map (
  22                         PHYS_INSTR_ADDR_WIDTH,
  23                         WORD_WIDTH
  24                 )
  25
  26                 port map (
  27                         clk,
  28                         instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  29                         instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  30                         instr_we,
  31                         instr_wr_data,
  32                         instr_rd_data
  33                 );
  34
  35 syn: process(clk, reset)
  36
  37 begin
  38
  39         if (reset = RESET_VALUE) then
  40                 instr_r_addr <= (others => '0');
  41         elsif rising_edge(clk) then
  42                 instr_r_addr <= instr_r_addr_nxt;
  43         end if;
  44
  45 end process;
  46
  47
  48 asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
  49
  50 begin
  51
  52         instruction <= instr_rd_data;
  53         instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
  54
  55         if (alu_jump_bit = LOGIC_ACT) then
  56                 instr_r_addr_nxt <= jump_result;
  57         elsif (branch_prediction_bit = LOGIC_ACT) then
  58                 instr_r_addr_nxt <= prediction_result;
  59         end if;
  60
  61 end process;
  62
  63 end behav;
  64