3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
7 use work.extension_pkg.all;
9 package extension_uart_pkg is
17 constant UART_WIDTH : integer := 8;
18 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
19 constant BAUD_RATE_WIDTH : integer := 16;
20 subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
22 --constant CLK_FREQ_MHZ : real := 33.33;
23 --constant BAUD_RATE : integer := 115200;
24 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
25 -- constant CLK_PER_BAUD : integer := 434;
26 constant CLK_PER_BAUD : integer := 173; -- @uni, bei 20MHz und 115200 Baud
28 component extension_uart is
29 --some modules won't need all inputs/outputs
32 RESET_VALUE : std_logic
38 -- general extension interface
39 ext_reg : in extmod_rec;
40 data_out : out gp_register_t;
42 uart_int : out std_logic;
44 bus_rx : in std_logic;
46 bus_tx : out std_logic
48 end component extension_uart;
53 RESET_VALUE : std_logic
58 sys_clk : in std_logic;
59 sys_res_n : in std_logic;
62 bus_tx : out std_logic;
65 new_tx_data : in std_logic;
66 tx_data : in uart_data;
67 tx_rdy : out std_logic;
68 bd_rate : in baud_rate_l;
69 stop_bit : in std_logic
71 end component rs232_tx;
76 RESET_VALUE : std_logic;
77 SYNC_STAGES : integer range 2 to integer'high
82 sys_clk : in std_logic;
83 sys_res_n : in std_logic;
86 bus_rx_unsync : in std_logic;
89 new_rx_data : out std_logic;
90 rx_data : out uart_data;
91 bd_rate : in baud_rate_l
93 end component rs232_rx;
97 end package extension_uart_pkg;