2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
17 signal rx_data : std_logic_vector(7 downto 0);
19 signal uart_int_nxt : std_logic;
21 signal uart_data_read, uart_data_read_nxt : std_logic;
26 rs232_tx_inst : rs232_tx
40 w3_uart_send(byte_t'range),
46 rs232_rx_inst : rs232_rx
68 syn : process (clk, reset)
70 if (reset = RESET_VALUE) then
71 w1_st_co <= (others=>'0');
72 w2_uart_config(31 downto 16) <= (others=>'0');
73 -- todo mit einer konstante versehen
74 w2_uart_config(15 downto 0) <= std_logic_vector(unsigned(CLK_PER_BAUD)); -- x"01B2";
75 w3_uart_send <= (others=>'0');
76 w4_uart_receive <= (others=>'0');
79 uart_data_read <= '0';
82 elsif rising_edge(clk) then
83 w1_st_co <= w1_st_co_nxt;
84 w2_uart_config <= w2_uart_config_nxt;
85 w3_uart_send <= w3_uart_send_nxt;
86 w4_uart_receive <= w4_uart_receive_nxt;
87 new_tx_data <= new_tx_data_nxt;
89 uart_data_read <= uart_data_read_nxt;
90 uart_int <= uart_int_nxt;
94 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
96 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
98 variable tmp_data : gp_register_t;
102 w1_st_co_nxt <= w1_st_co;
103 w2_uart_config_nxt <= w2_uart_config;
104 w3_uart_send_nxt <= w3_uart_send;
105 w4_uart_receive_nxt <= w4_uart_receive;
107 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
108 tmp_data := (others =>'0');
109 if ext_reg.byte_en(0) = '1' then
110 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
112 if ext_reg.byte_en(1) = '1' then
113 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
115 if ext_reg.byte_en(2) = '1' then
116 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
118 if ext_reg.byte_en(3) = '1' then
119 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
122 case ext_reg.addr(1 downto 0) is
124 w1_st_co_nxt <= tmp_data;
126 w2_uart_config_nxt <= tmp_data;
128 w1_st_co_nxt(16) <= '1'; -- busy flag set
129 w3_uart_send_nxt <= tmp_data;
131 --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
136 if tx_rdy = '1' and tx_rdy_int = '0' then
137 w1_st_co_nxt(16) <= '0'; -- busy flag reset
140 if new_bus_rx = '1' then
141 w4_uart_receive_nxt(7 downto 0) <= rx_data;
142 w1_st_co_nxt(17) <= '1';
146 if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
147 w1_st_co_nxt(17) <= '0';
152 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
154 variable tmp_data : gp_register_t;
158 uart_data_read_nxt <= '0';
160 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
161 case ext_reg.addr(1 downto 0) is
163 tmp_data := (others =>'0');
164 if ext_reg.byte_en(0) = '1' then
165 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
167 if ext_reg.byte_en(1) = '1' then
168 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
170 if ext_reg.byte_en(2) = '1' then
171 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
173 if ext_reg.byte_en(3) = '1' then
174 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
176 data_out <= tmp_data;
178 tmp_data := (others =>'0');
179 if ext_reg.byte_en(0) = '1' then
180 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
182 if ext_reg.byte_en(1) = '1' then
183 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
185 if ext_reg.byte_en(2) = '1' then
186 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
188 if ext_reg.byte_en(3) = '1' then
189 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
191 data_out <= tmp_data;
193 tmp_data := (others =>'0');
194 if ext_reg.byte_en(0) = '1' then
195 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
197 if ext_reg.byte_en(1) = '1' then
198 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
200 if ext_reg.byte_en(2) = '1' then
201 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
203 if ext_reg.byte_en(3) = '1' then
204 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
206 data_out <= tmp_data;
208 tmp_data := (others =>'0');
209 uart_data_read_nxt <= '1';
210 if ext_reg.byte_en(0) = '1' then
211 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
213 if ext_reg.byte_en(1) = '1' then
214 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
216 if ext_reg.byte_en(2) = '1' then
217 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
219 if ext_reg.byte_en(3) = '1' then
220 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
222 data_out <= tmp_data;
226 data_out <= (others=>'0');
231 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
233 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
235 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
240 new_tx_data_nxt <= '0';
241 bd_rate <= w2_uart_config(15 downto 0);
243 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
244 case ext_reg.addr(1 downto 0) is
250 new_tx_data_nxt <= '1';
257 end process dataprocess;
261 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------