cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17
  18 begin
  19
  20
  21 rs232_tx_inst : rs232_tx
  22 generic map(
  23                 RESET_VALUE
  24                 )
  25 port map(
  26         --System inputs
  27         clk,
  28         reset,
  29
  30         --Bus
  31         bus_tx,
  32
  33         --From/to sendlogic
  34         new_tx_data,
  35         w3_uart_send(byte_t'range),
  36         tx_rdy,
  37         bd_rate,
  38         w1_st_co(0)
  39 );
  40
  41
  42
  43
  44
  45 syn : process (clk, reset)
  46 begin
  47         if (reset = RESET_VALUE) then
  48                 w1_st_co <= (others=>'0');
  49                 w2_uart_config <= (others=>'0');
  50                 w3_uart_send <= (others=>'0');
  51                 w4_uart_receive <= (others=>'0');
  52
  53
  54         elsif rising_edge(clk) then
  55                 w1_st_co <= w1_st_co_nxt;
  56                 w2_uart_config <= w2_uart_config_nxt;
  57                 w3_uart_send <= w3_uart_send_nxt;
  58                 w4_uart_receive <= w4_uart_receive_nxt;
  59                 new_tx_data <= new_tx_data_nxt;
  60                 tx_rdy_int <= tx_rdy;
  61         end if;
  62 end process syn;
  63
  64 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  65
  66 gwriten : process (ext_reg,tx_rdy)
  67
  68 variable tmp_data  : gp_register_t;
  69
  70 begin
  71         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
  72                 tmp_data := (others =>'0');
  73                 if ext_reg.byte_en(0) = '1' then
  74                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
  75                 end if;
  76                 if ext_reg.byte_en(1) = '1' then
  77                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
  78                 end if;
  79                 if ext_reg.byte_en(2) = '1' then
  80                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
  81                 end if;
  82                 if ext_reg.byte_en(3) = '1' then
  83                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
  84                 end if;
  85
  86                 case ext_reg.addr(1 downto 0) is
  87                 when "00" =>
  88                         w1_st_co_nxt <= tmp_data;
  89                 when "01" =>
  90                         w2_uart_config_nxt <= tmp_data;
  91                 when "10" =>
  92                         w1_st_co_nxt(16) <= '1'; -- busy flag set
  93                         w3_uart_send_nxt <= tmp_data;
  94                 when "11" =>
  95                         w4_uart_receive_nxt <= tmp_data;
  96                 when others => null;
  97                 end case;
  98         else
  99                 w1_st_co_nxt <= w1_st_co;
 100                 w2_uart_config_nxt <= w2_uart_config;
 101                 w3_uart_send_nxt <= w3_uart_send;
 102                 w4_uart_receive_nxt <= w4_uart_receive;
 103         end if;
 104
 105         if  tx_rdy = '1' and tx_rdy_int = '0' then
 106                 w1_st_co_nxt(16) <= '0'; -- busy flag reset
 107         end if;
 108
 109 end process gwriten;
 110
 111 gread : process (clk,ext_reg)
 112
 113 variable tmp_data  : gp_register_t;
 114
 115 begin
 116         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 117                 case ext_reg.addr(1 downto 0) is
 118                 when "00" =>
 119                         tmp_data := (others =>'0');
 120                         if ext_reg.byte_en(0) = '1' then
 121                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 122                         end if;
 123                         if ext_reg.byte_en(1) = '1' then
 124                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 125                         end if;
 126                         if ext_reg.byte_en(2) = '1' then
 127                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 128                         end if;
 129                         if ext_reg.byte_en(3) = '1' then
 130                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 131                         end if;
 132                         data_out <= tmp_data;
 133                 when "01" =>
 134                         tmp_data := (others =>'0');
 135                         if ext_reg.byte_en(0) = '1' then
 136                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 137                         end if;
 138                         if ext_reg.byte_en(1) = '1' then
 139                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 140                         end if;
 141                         if ext_reg.byte_en(2) = '1' then
 142                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 143                         end if;
 144                         if ext_reg.byte_en(3) = '1' then
 145                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 146                         end if;
 147                         data_out <= tmp_data;
 148                 when "10" =>
 149                         tmp_data := (others =>'0');
 150                         if ext_reg.byte_en(0) = '1' then
 151                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 152                         end if;
 153                         if ext_reg.byte_en(1) = '1' then
 154                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 155                         end if;
 156                         if ext_reg.byte_en(2) = '1' then
 157                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 158                         end if;
 159                         if ext_reg.byte_en(3) = '1' then
 160                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 161                         end if;
 162                         data_out <= tmp_data;
 163                 when "11" =>
 164                         tmp_data := (others =>'0');
 165                         if ext_reg.byte_en(0) = '1' then
 166                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 167                         end if;
 168                         if ext_reg.byte_en(1) = '1' then
 169                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 170                         end if;
 171                         if ext_reg.byte_en(2) = '1' then
 172                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 173                         end if;
 174                         if ext_reg.byte_en(3) = '1' then
 175                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 176                         end if;
 177                         data_out <= tmp_data;
 178                 when others => null;
 179                 end case;
 180         else
 181                 data_out  <= (others=>'0');
 182         end if;
 183 end process gread;
 184
 185
 186 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 187
 188 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 189
 190 dataprocess : process (ext_reg,tx_rdy)
 191
 192
 193 begin
 194
 195         new_tx_data_nxt <= '0';
 196         bd_rate <= w2_uart_config(15 downto 0);
 197
 198         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 199                 case ext_reg.addr(1 downto 0) is
 200                 when "00" =>
 201
 202                 when "01" =>
 203
 204                 when "10" =>
 205                         new_tx_data_nxt <= '1';
 206                 when "11" =>
 207
 208                 when others => null;
 209                 end case;
 210         end if;
 211
 212 end process dataprocess;
 213
 214
 215
 216 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 217
 218 end behav;
 219