2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
17 signal rx_data : std_logic_vector(7 downto 0);
19 signal uart_int_nxt : std_logic;
20 signal uart_data_read_nxt : std_logic;
25 rs232_tx_inst : rs232_tx
39 w3_uart_send(byte_t'range),
45 rs232_rx_inst : rs232_rx
67 syn : process (clk, reset)
69 if (reset = RESET_VALUE) then
70 w1_st_co <= (others=>'0');
71 w2_uart_config(31 downto 16) <= (others=>'0');
72 w2_uart_config(15 downto 0) <= x"01b2"; -- std_logic_vector(to_unsigned(CLK_PER_BAUD, 16)); -- x"0822"; -- x"01B2";
73 w3_uart_send <= (others=>'0');
74 w4_uart_receive <= (others=>'0');
79 elsif rising_edge(clk) then
80 w1_st_co <= w1_st_co_nxt;
81 w2_uart_config <= w2_uart_config_nxt;
82 w3_uart_send <= w3_uart_send_nxt;
83 w4_uart_receive <= w4_uart_receive_nxt;
84 new_tx_data <= new_tx_data_nxt;
86 uart_int <= uart_int_nxt;
90 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
93 (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
95 variable tmp_data : gp_register_t;
99 w1_st_co_nxt <= w1_st_co;
100 w2_uart_config_nxt <= w2_uart_config;
101 w3_uart_send_nxt <= w3_uart_send;
102 w4_uart_receive_nxt <= w4_uart_receive;
104 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
105 tmp_data := (others =>'0');
106 if ext_reg.byte_en(0) = '1' then
107 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
109 if ext_reg.byte_en(1) = '1' then
110 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
112 if ext_reg.byte_en(2) = '1' then
113 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
115 if ext_reg.byte_en(3) = '1' then
116 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
119 case ext_reg.addr(1 downto 0) is
121 w1_st_co_nxt <= tmp_data;
123 w2_uart_config_nxt <= tmp_data;
125 w1_st_co_nxt(0) <= '1'; -- busy flag set
126 w3_uart_send_nxt <= tmp_data;
128 --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
133 if tx_rdy = '1' and tx_rdy_int = '0' then
134 w1_st_co_nxt(0) <= '0'; -- busy flag reset
137 if new_bus_rx = '1' then
138 w4_uart_receive_nxt(7 downto 0) <= rx_data;
139 w1_st_co_nxt(1) <= '1';
143 if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
144 w1_st_co_nxt(1) <= '0';
149 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
151 variable tmp_data : gp_register_t;
155 uart_data_read_nxt <= '0';
157 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
158 case ext_reg.addr(1 downto 0) is
160 tmp_data := (others =>'0');
161 if ext_reg.byte_en(0) = '1' then
162 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
164 if ext_reg.byte_en(1) = '1' then
165 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
167 if ext_reg.byte_en(2) = '1' then
168 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
170 if ext_reg.byte_en(3) = '1' then
171 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
173 data_out <= tmp_data;
175 tmp_data := (others =>'0');
176 if ext_reg.byte_en(0) = '1' then
177 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
179 if ext_reg.byte_en(1) = '1' then
180 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
182 if ext_reg.byte_en(2) = '1' then
183 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
185 if ext_reg.byte_en(3) = '1' then
186 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
188 data_out <= tmp_data;
190 tmp_data := (others =>'0');
191 if ext_reg.byte_en(0) = '1' then
192 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
194 if ext_reg.byte_en(1) = '1' then
195 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
197 if ext_reg.byte_en(2) = '1' then
198 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
200 if ext_reg.byte_en(3) = '1' then
201 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
203 data_out <= tmp_data;
205 tmp_data := (others =>'0');
206 uart_data_read_nxt <= '1';
207 if ext_reg.byte_en(0) = '1' then
208 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
210 if ext_reg.byte_en(1) = '1' then
211 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
213 if ext_reg.byte_en(2) = '1' then
214 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
216 if ext_reg.byte_en(3) = '1' then
217 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
219 data_out <= tmp_data;
223 data_out <= (others=>'0');
228 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
230 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
232 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
237 new_tx_data_nxt <= '0';
238 bd_rate <= w2_uart_config(15 downto 0);
240 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
241 case ext_reg.addr(1 downto 0) is
247 new_tx_data_nxt <= '1';
254 end process dataprocess;
258 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------