cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17 signal rx_data : std_logic_vector(7 downto 0);
  18
  19 signal uart_int_nxt : std_logic;
  20 signal uart_data_read_nxt : std_logic;
  21
  22 begin
  23
  24
  25 rs232_tx_inst : rs232_tx
  26 generic map(
  27                 RESET_VALUE
  28                 )
  29 port map(
  30         --System inputs
  31         clk,
  32         reset,
  33
  34         --Bus
  35         bus_tx,
  36
  37         --From/to sendlogic
  38         new_tx_data,
  39         w3_uart_send(byte_t'range),
  40         tx_rdy,
  41         bd_rate,
  42         w1_st_co(16)
  43 );
  44
  45 rs232_rx_inst : rs232_rx
  46 generic map(
  47                 RESET_VALUE,
  48                 2
  49                 )
  50 port map(
  51         --System inputs
  52         clk,
  53         reset,
  54
  55         --Bus
  56         bus_rx,
  57
  58         --From/to sendlogic
  59         new_bus_rx,
  60         rx_data,
  61         bd_rate
  62 );
  63
  64
  65
  66
  67 syn : process (clk, reset)
  68 begin
  69    if (reset = RESET_VALUE) then
  70                         w1_st_co <= (others=>'0');
  71                         w2_uart_config(31 downto 16) <= (others=>'0');
  72                         w2_uart_config(15 downto 0) <= x"01b2"; -- std_logic_vector(to_unsigned(CLK_PER_BAUD, 16)); -- x"0822"; -- x"01B2";
  73                         w3_uart_send <= (others=>'0');
  74                         w4_uart_receive <= (others=>'0');
  75                         tx_rdy_int <= '0';
  76                         new_tx_data <= '0';
  77                         uart_int <= '0';
  78
  79         elsif rising_edge(clk) then
  80                         w1_st_co <= w1_st_co_nxt;
  81                         w2_uart_config <= w2_uart_config_nxt;
  82                         w3_uart_send <= w3_uart_send_nxt;
  83                         w4_uart_receive <= w4_uart_receive_nxt;
  84                         new_tx_data <= new_tx_data_nxt;
  85                         tx_rdy_int <= tx_rdy;
  86                         uart_int <= uart_int_nxt;
  87    end if;
  88 end process syn;
  89
  90 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  91
  92 gwriten : process
  93         (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
  94
  95 variable tmp_data  : gp_register_t;
  96
  97 begin
  98                 uart_int_nxt <= '0';
  99                 w1_st_co_nxt <= w1_st_co;
 100                 w2_uart_config_nxt <= w2_uart_config;
 101                 w3_uart_send_nxt <= w3_uart_send;
 102                 w4_uart_receive_nxt <= w4_uart_receive;
 103
 104         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 105                 tmp_data := (others =>'0');
 106                 if ext_reg.byte_en(0) = '1' then
 107                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
 108                 end if;
 109                 if ext_reg.byte_en(1) = '1' then
 110                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 111                 end if;
 112                 if ext_reg.byte_en(2) = '1' then
 113                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 114                 end if;
 115                 if ext_reg.byte_en(3) = '1' then
 116                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 117                 end if;
 118
 119                 case ext_reg.addr(1 downto 0) is
 120                 when "00" =>
 121                         w1_st_co_nxt <= tmp_data;
 122                 when "01" =>
 123                         w2_uart_config_nxt <= tmp_data;
 124                 when "10" =>
 125                         w1_st_co_nxt(0) <= '1'; -- busy flag set
 126                         w3_uart_send_nxt <= tmp_data;
 127                 when "11" =>
 128                         --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 129                 when others => null;
 130                 end case;
 131         end if;
 132
 133         if  tx_rdy = '1' and tx_rdy_int = '0' then
 134                 w1_st_co_nxt(0) <= '0'; -- busy flag reset
 135         end if;
 136
 137         if new_bus_rx = '1' then
 138                 w4_uart_receive_nxt(7 downto 0) <= rx_data;
 139                 w1_st_co_nxt(1) <= '1';
 140                 uart_int_nxt <= '1';
 141         end if;
 142
 143         if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
 144                 w1_st_co_nxt(1) <= '0';
 145         end if;
 146
 147 end process gwriten;
 148
 149 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 150
 151 variable tmp_data  : gp_register_t;
 152
 153 begin
 154
 155         uart_data_read_nxt <= '0';
 156
 157         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 158                 case ext_reg.addr(1 downto 0) is
 159                 when "00" =>
 160                         tmp_data := (others =>'0');
 161                         if ext_reg.byte_en(0) = '1' then
 162                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 163                         end if;
 164                         if ext_reg.byte_en(1) = '1' then
 165                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 166                         end if;
 167                         if ext_reg.byte_en(2) = '1' then
 168                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 169                         end if;
 170                         if ext_reg.byte_en(3) = '1' then
 171                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 172                         end if;
 173                         data_out <= tmp_data;
 174                 when "01" =>
 175                         tmp_data := (others =>'0');
 176                         if ext_reg.byte_en(0) = '1' then
 177                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 178                         end if;
 179                         if ext_reg.byte_en(1) = '1' then
 180                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 181                         end if;
 182                         if ext_reg.byte_en(2) = '1' then
 183                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 184                         end if;
 185                         if ext_reg.byte_en(3) = '1' then
 186                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 187                         end if;
 188                         data_out <= tmp_data;
 189                 when "10" =>
 190                         tmp_data := (others =>'0');
 191                         if ext_reg.byte_en(0) = '1' then
 192                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 193                         end if;
 194                         if ext_reg.byte_en(1) = '1' then
 195                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 196                         end if;
 197                         if ext_reg.byte_en(2) = '1' then
 198                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 199                         end if;
 200                         if ext_reg.byte_en(3) = '1' then
 201                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 202                         end if;
 203                         data_out <= tmp_data;
 204                 when "11" =>
 205                         tmp_data := (others =>'0');
 206                         uart_data_read_nxt <= '1';
 207                         if ext_reg.byte_en(0) = '1' then
 208                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 209                         end if;
 210                         if ext_reg.byte_en(1) = '1' then
 211                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 212                         end if;
 213                         if ext_reg.byte_en(2) = '1' then
 214                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 215                         end if;
 216                         if ext_reg.byte_en(3) = '1' then
 217                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 218                         end if;
 219                         data_out <= tmp_data;
 220                 when others => null;
 221                 end case;
 222         else
 223                 data_out  <= (others=>'0');
 224         end if;
 225 end process gread;
 226
 227
 228 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 229
 230 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 231
 232 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 233
 234
 235 begin
 236
 237         new_tx_data_nxt <= '0';
 238         bd_rate <= w2_uart_config(15 downto 0);
 239
 240         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 241                 case ext_reg.addr(1 downto 0) is
 242                 when "00" =>
 243
 244                 when "01" =>
 245
 246                 when "10" =>
 247                         new_tx_data_nxt <= '1';
 248                 when "11" =>
 249
 250                 when others => null;
 251                 end case;
 252         end if;
 253
 254 end process dataprocess;
 255
 256
 257
 258 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 259
 260 end behav;
 261