2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
17 signal rx_data : std_logic_vector(7 downto 0);
21 rs232_tx_inst : rs232_tx
35 w3_uart_send(byte_t'range),
41 rs232_rx_inst : rs232_rx
62 syn : process (clk, reset)
64 if (reset = RESET_VALUE) then
65 w1_st_co <= (others=>'0');
66 w2_uart_config(31 downto 16) <= (others=>'0');
67 -- todo mit einer konstante versehen
68 w2_uart_config(15 downto 0) <= x"01B2";
69 w3_uart_send <= (others=>'0');
70 w4_uart_receive <= (others=>'0');
74 elsif rising_edge(clk) then
75 w1_st_co <= w1_st_co_nxt;
76 w2_uart_config <= w2_uart_config_nxt;
77 w3_uart_send <= w3_uart_send_nxt;
78 w4_uart_receive <= w4_uart_receive_nxt;
79 new_tx_data <= new_tx_data_nxt;
84 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
86 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
88 variable tmp_data : gp_register_t;
92 w1_st_co_nxt <= w1_st_co;
93 w2_uart_config_nxt <= w2_uart_config;
94 w3_uart_send_nxt <= w3_uart_send;
95 w4_uart_receive_nxt <= w4_uart_receive;
97 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
98 tmp_data := (others =>'0');
99 if ext_reg.byte_en(0) = '1' then
100 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
102 if ext_reg.byte_en(1) = '1' then
103 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
105 if ext_reg.byte_en(2) = '1' then
106 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
108 if ext_reg.byte_en(3) = '1' then
109 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
112 case ext_reg.addr(1 downto 0) is
114 w1_st_co_nxt <= tmp_data;
116 w2_uart_config_nxt <= tmp_data;
118 w1_st_co_nxt(16) <= '1'; -- busy flag set
119 w3_uart_send_nxt <= tmp_data;
121 --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
126 if tx_rdy = '1' and tx_rdy_int = '0' then
127 w1_st_co_nxt(16) <= '0'; -- busy flag reset
130 if new_bus_rx = '1' then
131 w4_uart_receive_nxt(7 downto 0) <= rx_data;
132 w1_st_co_nxt(17) <= '1';
138 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
140 variable tmp_data : gp_register_t;
143 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
144 case ext_reg.addr(1 downto 0) is
146 tmp_data := (others =>'0');
147 if ext_reg.byte_en(0) = '1' then
148 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
150 if ext_reg.byte_en(1) = '1' then
151 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
153 if ext_reg.byte_en(2) = '1' then
154 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
156 if ext_reg.byte_en(3) = '1' then
157 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
159 data_out <= tmp_data;
161 tmp_data := (others =>'0');
162 if ext_reg.byte_en(0) = '1' then
163 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
165 if ext_reg.byte_en(1) = '1' then
166 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
168 if ext_reg.byte_en(2) = '1' then
169 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
171 if ext_reg.byte_en(3) = '1' then
172 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
174 data_out <= tmp_data;
176 tmp_data := (others =>'0');
177 if ext_reg.byte_en(0) = '1' then
178 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
180 if ext_reg.byte_en(1) = '1' then
181 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
183 if ext_reg.byte_en(2) = '1' then
184 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
186 if ext_reg.byte_en(3) = '1' then
187 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
189 data_out <= tmp_data;
191 tmp_data := (others =>'0');
192 if ext_reg.byte_en(0) = '1' then
193 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
195 if ext_reg.byte_en(1) = '1' then
196 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
198 if ext_reg.byte_en(2) = '1' then
199 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
201 if ext_reg.byte_en(3) = '1' then
202 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
204 data_out <= tmp_data;
208 data_out <= (others=>'0');
213 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
215 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
217 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
222 new_tx_data_nxt <= '0';
223 bd_rate <= w2_uart_config(15 downto 0);
225 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
226 case ext_reg.addr(1 downto 0) is
232 new_tx_data_nxt <= '1';
239 end process dataprocess;
243 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------