cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17 signal rx_data : std_logic_vector(7 downto 0);
  18
  19 signal uart_int_nxt : std_logic;
  20
  21 signal uart_data_read, uart_data_read_nxt : std_logic;
  22
  23 begin
  24
  25
  26 rs232_tx_inst : rs232_tx
  27 generic map(
  28                 RESET_VALUE
  29                 )
  30 port map(
  31         --System inputs
  32         clk,
  33         reset,
  34
  35         --Bus
  36         bus_tx,
  37
  38         --From/to sendlogic
  39         new_tx_data,
  40         w3_uart_send(byte_t'range),
  41         tx_rdy,
  42         bd_rate,
  43         w1_st_co(16)
  44 );
  45
  46 rs232_rx_inst : rs232_rx
  47 generic map(
  48                 RESET_VALUE,
  49                 2
  50                 )
  51 port map(
  52         --System inputs
  53         clk,
  54         reset,
  55
  56         --Bus
  57         bus_rx,
  58
  59         --From/to sendlogic
  60         new_bus_rx,
  61         rx_data,
  62         bd_rate
  63 );
  64
  65
  66
  67
  68 syn : process (clk, reset)
  69 begin
  70    if (reset = RESET_VALUE) then
  71                         w1_st_co <= (others=>'0');
  72                         w2_uart_config(31 downto 16) <= (others=>'0');
  73                         w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16)); -- x"0822"; -- x"01B2";
  74                         w3_uart_send <= (others=>'0');
  75                         w4_uart_receive <= (others=>'0');
  76                         tx_rdy_int <= '0';
  77                         new_tx_data <= '0';
  78                         uart_data_read <= '0';
  79                         uart_int <= '0';
  80
  81         elsif rising_edge(clk) then
  82                         w1_st_co <= w1_st_co_nxt;
  83                         w2_uart_config <= w2_uart_config_nxt;
  84                         w3_uart_send <= w3_uart_send_nxt;
  85                         w4_uart_receive <= w4_uart_receive_nxt;
  86                         new_tx_data <= new_tx_data_nxt;
  87                         tx_rdy_int <= tx_rdy;
  88                         uart_data_read <= uart_data_read_nxt;
  89                         uart_int <= uart_int_nxt;
  90    end if;
  91 end process syn;
  92
  93 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  94
  95 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
  96
  97 variable tmp_data  : gp_register_t;
  98
  99 begin
 100                 uart_int_nxt <= '0';
 101                 w1_st_co_nxt <= w1_st_co;
 102                 w2_uart_config_nxt <= w2_uart_config;
 103                 w3_uart_send_nxt <= w3_uart_send;
 104                 w4_uart_receive_nxt <= w4_uart_receive;
 105
 106         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 107                 tmp_data := (others =>'0');
 108                 if ext_reg.byte_en(0) = '1' then
 109                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
 110                 end if;
 111                 if ext_reg.byte_en(1) = '1' then
 112                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 113                 end if;
 114                 if ext_reg.byte_en(2) = '1' then
 115                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 116                 end if;
 117                 if ext_reg.byte_en(3) = '1' then
 118                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 119                 end if;
 120
 121                 case ext_reg.addr(1 downto 0) is
 122                 when "00" =>
 123                         w1_st_co_nxt <= tmp_data;
 124                 when "01" =>
 125                         w2_uart_config_nxt <= tmp_data;
 126                 when "10" =>
 127                         w1_st_co_nxt(0) <= '1'; -- busy flag set
 128                         w3_uart_send_nxt <= tmp_data;
 129                 when "11" =>
 130                         --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 131                 when others => null;
 132                 end case;
 133         end if;
 134
 135         if  tx_rdy = '1' and tx_rdy_int = '0' then
 136                 w1_st_co_nxt(0) <= '0'; -- busy flag reset
 137         end if;
 138
 139         if new_bus_rx = '1' then
 140                 w4_uart_receive_nxt(7 downto 0) <= rx_data;
 141                 w1_st_co_nxt(1) <= '1';
 142                 uart_int_nxt <= '1';
 143         end if;
 144
 145         if (uart_data_read = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
 146                 w1_st_co_nxt(1) <= '0';
 147         end if;
 148
 149 end process gwriten;
 150
 151 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 152
 153 variable tmp_data  : gp_register_t;
 154
 155 begin
 156
 157         uart_data_read_nxt <= '0';
 158
 159         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 160                 case ext_reg.addr(1 downto 0) is
 161                 when "00" =>
 162                         tmp_data := (others =>'0');
 163                         if ext_reg.byte_en(0) = '1' then
 164                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 165                         end if;
 166                         if ext_reg.byte_en(1) = '1' then
 167                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 168                         end if;
 169                         if ext_reg.byte_en(2) = '1' then
 170                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 171                         end if;
 172                         if ext_reg.byte_en(3) = '1' then
 173                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 174                         end if;
 175                         data_out <= tmp_data;
 176                 when "01" =>
 177                         tmp_data := (others =>'0');
 178                         if ext_reg.byte_en(0) = '1' then
 179                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 180                         end if;
 181                         if ext_reg.byte_en(1) = '1' then
 182                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 183                         end if;
 184                         if ext_reg.byte_en(2) = '1' then
 185                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 186                         end if;
 187                         if ext_reg.byte_en(3) = '1' then
 188                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 189                         end if;
 190                         data_out <= tmp_data;
 191                 when "10" =>
 192                         tmp_data := (others =>'0');
 193                         if ext_reg.byte_en(0) = '1' then
 194                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 195                         end if;
 196                         if ext_reg.byte_en(1) = '1' then
 197                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 198                         end if;
 199                         if ext_reg.byte_en(2) = '1' then
 200                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 201                         end if;
 202                         if ext_reg.byte_en(3) = '1' then
 203                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 204                         end if;
 205                         data_out <= tmp_data;
 206                 when "11" =>
 207                         tmp_data := (others =>'0');
 208                         uart_data_read_nxt <= '1';
 209                         if ext_reg.byte_en(0) = '1' then
 210                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 211                         end if;
 212                         if ext_reg.byte_en(1) = '1' then
 213                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 214                         end if;
 215                         if ext_reg.byte_en(2) = '1' then
 216                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 217                         end if;
 218                         if ext_reg.byte_en(3) = '1' then
 219                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 220                         end if;
 221                         data_out <= tmp_data;
 222                 when others => null;
 223                 end case;
 224         else
 225                 data_out  <= (others=>'0');
 226         end if;
 227 end process gread;
 228
 229
 230 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 231
 232 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 233
 234 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 235
 236
 237 begin
 238
 239         new_tx_data_nxt <= '0';
 240         bd_rate <= w2_uart_config(15 downto 0);
 241
 242         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 243                 case ext_reg.addr(1 downto 0) is
 244                 when "00" =>
 245
 246                 when "01" =>
 247
 248                 when "10" =>
 249                         new_tx_data_nxt <= '1';
 250                 when "11" =>
 251
 252                 when others => null;
 253                 end case;
 254         end if;
 255
 256 end process dataprocess;
 257
 258
 259
 260 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 261
 262 end behav;
 263