cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17
  18 begin
  19
  20
  21 rs232_tx_inst : rs232_tx
  22 generic map(
  23                 RESET_VALUE
  24                 )
  25 port map(
  26         --System inputs
  27         clk,
  28         reset,
  29
  30         --Bus
  31         bus_tx,
  32
  33         --From/to sendlogic
  34         new_tx_data,
  35         w3_uart_send(byte_t'range),
  36         tx_rdy,
  37         bd_rate,
  38         w1_st_co(0)
  39 );
  40
  41 rs232_rx_inst : rs232_rx
  42 generic map(
  43                 RESET_VALUE
  44                 )
  45 port map(
  46         --System inputs
  47         clk,
  48         reset,
  49
  50         --Bus
  51         bus_rx,
  52
  53         --From/to sendlogic
  54         w1_st_co(17),
  55         w4_uart_receive(byte_t'range)
  56
  57 );
  58
  59
  60
  61
  62 syn : process (clk, reset)
  63 begin
  64         if (reset = RESET_VALUE) then
  65                 w1_st_co <= (others=>'0');
  66                 w2_uart_config <= (others=>'0');
  67                 w3_uart_send <= (others=>'0');
  68                 w4_uart_receive <= (others=>'0');
  69
  70
  71         elsif rising_edge(clk) then
  72                 w1_st_co <= w1_st_co_nxt;
  73                 w2_uart_config <= w2_uart_config_nxt;
  74                 w3_uart_send <= w3_uart_send_nxt;
  75                 w4_uart_receive <= w4_uart_receive_nxt;
  76                 new_tx_data <= new_tx_data_nxt;
  77                 tx_rdy_int <= tx_rdy;
  78         end if;
  79 end process syn;
  80
  81 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  82
  83 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
  84
  85 variable tmp_data  : gp_register_t;
  86
  87 begin
  88
  89                 w1_st_co_nxt <= w1_st_co;
  90                 w2_uart_config_nxt <= w2_uart_config;
  91                 w3_uart_send_nxt <= w3_uart_send;
  92                 w4_uart_receive_nxt <= w4_uart_receive;
  93
  94         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
  95                 tmp_data := (others =>'0');
  96                 if ext_reg.byte_en(0) = '1' then
  97                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
  98                 end if;
  99                 if ext_reg.byte_en(1) = '1' then
 100                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 101                 end if;
 102                 if ext_reg.byte_en(2) = '1' then
 103                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 104                 end if;
 105                 if ext_reg.byte_en(3) = '1' then
 106                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 107                 end if;
 108
 109                 case ext_reg.addr(1 downto 0) is
 110                 when "00" =>
 111                         w1_st_co_nxt <= tmp_data;
 112                 when "01" =>
 113                         w2_uart_config_nxt <= tmp_data;
 114                 when "10" =>
 115                         w1_st_co_nxt(16) <= '1'; -- busy flag set
 116                         w3_uart_send_nxt <= tmp_data;
 117                 when "11" =>
 118                         w4_uart_receive_nxt <= tmp_data;
 119                 when others => null;
 120                 end case;
 121         end if;
 122
 123         if  tx_rdy = '1' and tx_rdy_int = '0' then
 124                 w1_st_co_nxt(16) <= '0'; -- busy flag reset
 125         end if;
 126
 127 end process gwriten;
 128
 129 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 130
 131 variable tmp_data  : gp_register_t;
 132
 133 begin
 134         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 135                 case ext_reg.addr(1 downto 0) is
 136                 when "00" =>
 137                         tmp_data := (others =>'0');
 138                         if ext_reg.byte_en(0) = '1' then
 139                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 140                         end if;
 141                         if ext_reg.byte_en(1) = '1' then
 142                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 143                         end if;
 144                         if ext_reg.byte_en(2) = '1' then
 145                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 146                         end if;
 147                         if ext_reg.byte_en(3) = '1' then
 148                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 149                         end if;
 150                         data_out <= tmp_data;
 151                 when "01" =>
 152                         tmp_data := (others =>'0');
 153                         if ext_reg.byte_en(0) = '1' then
 154                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 155                         end if;
 156                         if ext_reg.byte_en(1) = '1' then
 157                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 158                         end if;
 159                         if ext_reg.byte_en(2) = '1' then
 160                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 161                         end if;
 162                         if ext_reg.byte_en(3) = '1' then
 163                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 164                         end if;
 165                         data_out <= tmp_data;
 166                 when "10" =>
 167                         tmp_data := (others =>'0');
 168                         if ext_reg.byte_en(0) = '1' then
 169                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 170                         end if;
 171                         if ext_reg.byte_en(1) = '1' then
 172                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 173                         end if;
 174                         if ext_reg.byte_en(2) = '1' then
 175                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 176                         end if;
 177                         if ext_reg.byte_en(3) = '1' then
 178                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 179                         end if;
 180                         data_out <= tmp_data;
 181                 when "11" =>
 182                         tmp_data := (others =>'0');
 183                         if ext_reg.byte_en(0) = '1' then
 184                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 185                         end if;
 186                         if ext_reg.byte_en(1) = '1' then
 187                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 188                         end if;
 189                         if ext_reg.byte_en(2) = '1' then
 190                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 191                         end if;
 192                         if ext_reg.byte_en(3) = '1' then
 193                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 194                         end if;
 195                         data_out <= tmp_data;
 196                 when others => null;
 197                 end case;
 198         else
 199                 data_out  <= (others=>'0');
 200         end if;
 201 end process gread;
 202
 203
 204 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 205
 206 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 207
 208 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 209
 210
 211 begin
 212
 213         new_tx_data_nxt <= '0';
 214         bd_rate <= w2_uart_config(15 downto 0);
 215
 216         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 217                 case ext_reg.addr(1 downto 0) is
 218                 when "00" =>
 219
 220                 when "01" =>
 221
 222                 when "10" =>
 223                         new_tx_data_nxt <= '1';
 224                 when "11" =>
 225
 226                 when others => null;
 227                 end case;
 228         end if;
 229
 230 end process dataprocess;
 231
 232
 233
 234 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 235
 236 end behav;
 237