1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
27 use work.extension_pkg.all;
29 architecture behav of extension_interrupt is
31 signal w1_st_co, w1_st_co_nxt, w2_int_config, w2_int_config_nxt : gp_register_t;
35 syn : process (clk, reset)
37 if (reset = RESET_VALUE) then
38 w1_st_co <= (others=>'0');
39 w2_int_config(31 downto 0) <= (others=>'0');
40 -- todo mit einer konstante versehen
42 elsif rising_edge(clk) then
43 w1_st_co <= w1_st_co_nxt;
44 w2_int_config <= w2_int_config_nxt;
48 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
50 gwriten : process (ext_reg,w1_st_co,w2_int_config)
52 variable tmp_data : gp_register_t;
56 w1_st_co_nxt <= w1_st_co;
57 w2_int_config_nxt <= w2_int_config;
59 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
60 tmp_data := (others =>'0');
61 if ext_reg.byte_en(0) = '1' then
62 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
64 if ext_reg.byte_en(1) = '1' then
65 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
67 if ext_reg.byte_en(2) = '1' then
68 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
70 if ext_reg.byte_en(3) = '1' then
71 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
74 case ext_reg.addr(1 downto 0) is
76 w1_st_co_nxt <= tmp_data;
78 w2_int_config_nxt <= tmp_data;
85 gread : process (clk,ext_reg,w1_st_co,w2_int_config)
87 variable tmp_data : gp_register_t;
91 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
92 case ext_reg.addr(1 downto 0) is
94 tmp_data := (others =>'0');
95 if ext_reg.byte_en(0) = '1' then
96 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
98 if ext_reg.byte_en(1) = '1' then
99 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
101 if ext_reg.byte_en(2) = '1' then
102 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
104 if ext_reg.byte_en(3) = '1' then
105 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
107 data_out <= tmp_data;
109 tmp_data := (others =>'0');
110 if ext_reg.byte_en(0) = '1' then
111 tmp_data(byte_t'range) := w2_int_config(byte_t'range);
113 if ext_reg.byte_en(1) = '1' then
114 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_int_config((2*byte_t'length-1) downto byte_t'length);
116 if ext_reg.byte_en(2) = '1' then
117 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_int_config((3*byte_t'length-1) downto 2*byte_t'length);
119 if ext_reg.byte_en(3) = '1' then
120 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_int_config((4*byte_t'length-1) downto 3*byte_t'length);
122 data_out <= tmp_data;
123 when others => data_out <= (others => '0');
126 data_out <= (others=>'0');
131 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
133 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
135 dataprocess : process (w2_int_config, uart_int)
141 if (w2_int_config(GLOBAL_INT_EN_BIT) = '1') then
142 if (w2_int_config(UART_INT_EN_BIT) = '1' and uart_int = '1') then
147 end process dataprocess;
151 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------