cpu/src/extension_interrupt_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.extension_pkg.all;
   7
   8 architecture behav of extension_interrupt is
   9
  10 signal w1_st_co, w1_st_co_nxt, w2_int_config, w2_int_config_nxt : gp_register_t;
  11
  12 begin
  13
  14 syn : process (clk, reset)
  15 begin
  16    if (reset = RESET_VALUE) then
  17                         w1_st_co <= (others=>'0');
  18                         w2_int_config(31 downto 0) <= (others=>'0');
  19                         -- todo mit einer konstante versehen
  20
  21         elsif rising_edge(clk) then
  22                         w1_st_co <= w1_st_co_nxt;
  23                         w2_int_config <= w2_int_config_nxt;
  24    end if;
  25 end process syn;
  26
  27 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  28
  29 gwriten : process (ext_reg,w1_st_co,w2_int_config)
  30
  31 variable tmp_data  : gp_register_t;
  32
  33 begin
  34
  35         w1_st_co_nxt <= w1_st_co;
  36         w2_int_config_nxt <= w2_int_config;
  37
  38         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
  39                 tmp_data := (others =>'0');
  40                 if ext_reg.byte_en(0) = '1' then
  41                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
  42                 end if;
  43                 if ext_reg.byte_en(1) = '1' then
  44                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
  45                 end if;
  46                 if ext_reg.byte_en(2) = '1' then
  47                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
  48                 end if;
  49                 if ext_reg.byte_en(3) = '1' then
  50                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
  51                 end if;
  52
  53                 case ext_reg.addr(1 downto 0) is
  54                 when "00" =>
  55                         w1_st_co_nxt <= tmp_data;
  56                 when "01" =>
  57                         w2_int_config_nxt <= tmp_data;
  58                 when others => null;
  59                 end case;
  60         end if;
  61
  62 end process gwriten;
  63
  64 gread : process (clk,ext_reg,w1_st_co,w2_int_config)
  65
  66 variable tmp_data  : gp_register_t;
  67
  68 begin
  69
  70         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
  71                 case ext_reg.addr(1 downto 0) is
  72                 when "00" =>
  73                         tmp_data := (others =>'0');
  74                         if ext_reg.byte_en(0) = '1' then
  75                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
  76                         end if;
  77                         if ext_reg.byte_en(1) = '1' then
  78                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
  79                         end if;
  80                         if ext_reg.byte_en(2) = '1' then
  81                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
  82                         end if;
  83                         if ext_reg.byte_en(3) = '1' then
  84                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
  85                         end if;
  86                         data_out <= tmp_data;
  87                 when "01" =>
  88                         tmp_data := (others =>'0');
  89                         if ext_reg.byte_en(0) = '1' then
  90                                 tmp_data(byte_t'range) := w2_int_config(byte_t'range);
  91                         end if;
  92                         if ext_reg.byte_en(1) = '1' then
  93                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_int_config((2*byte_t'length-1) downto byte_t'length);
  94                         end if;
  95                         if ext_reg.byte_en(2) = '1' then
  96                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_int_config((3*byte_t'length-1) downto 2*byte_t'length);
  97                         end if;
  98                         if ext_reg.byte_en(3) = '1' then
  99                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_int_config((4*byte_t'length-1) downto 3*byte_t'length);
 100                         end if;
 101                         data_out <= tmp_data;
 102                 when others => data_out <= (others => '0');
 103                 end case;
 104         else
 105                 data_out  <= (others=>'0');
 106         end if;
 107 end process gread;
 108
 109
 110 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 111
 112 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 113
 114 dataprocess : process (w2_int_config, uart_int)
 115
 116 begin
 117
 118         int_req <= IDLE;
 119
 120         if (w2_int_config(GLOBAL_INT_EN_BIT) = '1') then
 121                 if (w2_int_config(UART_INT_EN_BIT) = '1' and uart_int = '1') then
 122                         int_req <= UART;
 123                 end if;
 124         end if;
 125
 126 end process dataprocess;
 127
 128
 129
 130 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 131
 132 end behav;
 133