2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 use IEEE.STD_LOGIC_ARITH.ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.ALL;
7 use work.common_pkg.all;
12 use work.extension_pkg.all;
13 use work.extension_imp_pkg.all;
15 architecture behav of extension_imp is
17 signal w1_st_co, w1_st_co_nxt, w2_im_addr, w2_im_addr_nxt, w3_im_data, w3_im_data_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;
18 signal new_im_data, new_im_data_nxt: std_logic;
23 syn : process (clk, reset)
25 if (reset = RESET_VALUE) then
26 w1_st_co <= (others=>'0');
27 w2_im_addr(31 downto 16) <= (others=>'0');
28 -- todo mit einer konstante versehen
29 w2_im_addr(15 downto 0) <= x"0003";
30 w3_im_data <= (others=>'0');
31 w4_im_notused <= (others=>'0');
36 elsif rising_edge(clk) then
37 w1_st_co <= w1_st_co_nxt;
38 w2_im_addr <= w2_im_addr_nxt;
39 w3_im_data <= w3_im_data_nxt;
40 w4_im_notused <= w4_im_notused_nxt;
42 new_im_data <= new_im_data_nxt;
47 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
49 gwriten : process (ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused)
51 variable tmp_data : gp_register_t;
55 w1_st_co_nxt <= w1_st_co;
56 w2_im_addr_nxt <= w2_im_addr;
57 w3_im_data_nxt <= w3_im_data;
58 w4_im_notused_nxt <= w4_im_notused;
60 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
61 tmp_data := (others =>'0');
62 if ext_reg.byte_en(0) = '1' then
63 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
65 if ext_reg.byte_en(1) = '1' then
66 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
68 if ext_reg.byte_en(2) = '1' then
69 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
71 if ext_reg.byte_en(3) = '1' then
72 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
75 case ext_reg.addr(1 downto 0) is
77 w1_st_co_nxt <= tmp_data;
79 -- -1 wegen increment des addr registers
80 tmp_data := tmp_data - '1';
81 w2_im_addr_nxt <= tmp_data;
83 w1_st_co_nxt(0) <= '1'; -- busy flag set
84 w2_im_addr_nxt <= w2_im_addr + '1';
85 w3_im_data_nxt <= tmp_data;
87 --w4_im_notused_nxt <= tmp_data; sollte nur gelesen werden
94 gread : process (clk,ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused)
96 variable tmp_data : gp_register_t;
99 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
100 case ext_reg.addr(1 downto 0) is
102 tmp_data := (others =>'0');
103 if ext_reg.byte_en(0) = '1' then
104 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
106 if ext_reg.byte_en(1) = '1' then
107 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
109 if ext_reg.byte_en(2) = '1' then
110 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
112 if ext_reg.byte_en(3) = '1' then
113 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
115 data_out <= tmp_data;
117 tmp_data := (others =>'0');
118 if ext_reg.byte_en(0) = '1' then
119 tmp_data(byte_t'range) := w2_im_addr(byte_t'range);
121 if ext_reg.byte_en(1) = '1' then
122 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_im_addr((2*byte_t'length-1) downto byte_t'length);
124 if ext_reg.byte_en(2) = '1' then
125 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_im_addr((3*byte_t'length-1) downto 2*byte_t'length);
127 if ext_reg.byte_en(3) = '1' then
128 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_im_addr((4*byte_t'length-1) downto 3*byte_t'length);
130 data_out <= tmp_data;
132 tmp_data := (others =>'0');
133 if ext_reg.byte_en(0) = '1' then
134 tmp_data(byte_t'range) := w3_im_data(byte_t'range);
136 if ext_reg.byte_en(1) = '1' then
137 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_im_data((2*byte_t'length-1) downto byte_t'length);
139 if ext_reg.byte_en(2) = '1' then
140 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_im_data((3*byte_t'length-1) downto 2*byte_t'length);
142 if ext_reg.byte_en(3) = '1' then
143 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_im_data((4*byte_t'length-1) downto 3*byte_t'length);
145 data_out <= tmp_data;
147 tmp_data := (others =>'0');
148 if ext_reg.byte_en(0) = '1' then
149 tmp_data(byte_t'range) := w4_im_notused(byte_t'range);
151 if ext_reg.byte_en(1) = '1' then
152 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_im_notused((2*byte_t'length-1) downto byte_t'length);
154 if ext_reg.byte_en(2) = '1' then
155 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_im_notused((3*byte_t'length-1) downto 2*byte_t'length);
157 if ext_reg.byte_en(3) = '1' then
158 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_im_notused((4*byte_t'length-1) downto 3*byte_t'length);
160 data_out <= tmp_data;
164 data_out <= (others=>'0');
169 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
171 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
173 dataprocess : process (ext_reg)
177 new_im_data_nxt <= '0';
178 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
179 case ext_reg.addr(1 downto 0) is
185 new_im_data_nxt <= '1';
192 end process dataprocess;
193 -- asyncrone verarbeitung
194 im_addr <= w2_im_addr;
195 im_data <= w3_im_data;
196 new_im_data_out <= new_im_data;
201 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------