1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
27 use work.extension_pkg.all;
29 package extension_7seg_pkg is
31 constant SEGMENT_G : std_logic_vector(0 to 6) := "0000001";
32 constant SEGMENT_F : std_logic_vector(0 to 6) := "0000010";
33 constant SEGMENT_E : std_logic_vector(0 to 6) := "0000100";
34 constant SEGMENT_D : std_logic_vector(0 to 6) := "0001000";
35 constant SEGMENT_C : std_logic_vector(0 to 6) := "0010000";
36 constant SEGMENT_B : std_logic_vector(0 to 6) := "0100000";
37 constant SEGMENT_A : std_logic_vector(0 to 6) := "1000000";
39 constant DIGIT_0 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F;
40 constant DIGIT_1 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C;
41 constant DIGIT_2 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D;
42 constant DIGIT_3 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_G;
43 constant DIGIT_4 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C or SEGMENT_G or SEGMENT_F;
44 constant DIGIT_5 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_G or SEGMENT_C or SEGMENT_D;
45 constant DIGIT_6 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
46 constant DIGIT_7 : std_logic_vector(0 to 6) := SEGMENT_A or DIGIT_1;
47 constant DIGIT_8 : std_logic_vector(0 to 6) := SEGMENT_G or DIGIT_0;
48 constant DIGIT_9 : std_logic_vector(0 to 6) := SEGMENT_B or DIGIT_5;
49 constant DIGIT_A : std_logic_vector(0 to 6) := DIGIT_1 or SEGMENT_A or SEGMENT_G or SEGMENT_E or SEGMENT_F;
50 constant DIGIT_B : std_logic_vector(0 to 6) := SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
51 constant DIGIT_C : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D;
52 constant DIGIT_D : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D or SEGMENT_C;
53 constant DIGIT_E : std_logic_vector(0 to 6) := DIGIT_C or SEGMENT_G;
54 constant DIGIT_F : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_G;
55 constant DIGIT_MINUS : std_logic_vector(0 to 6) := SEGMENT_G;
56 constant DIGIT_CLEAR : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F or SEGMENT_G;
58 subtype sseg_digit is std_logic_vector(4 downto 0);
60 type sseg_state_rec is record
61 digit0 : std_logic_vector(0 to 6);
62 digit1 : std_logic_vector(0 to 6);
63 digit2 : std_logic_vector(0 to 6);
64 digit3 : std_logic_vector(0 to 6);
67 function digit_decode(value : sseg_digit) return std_logic_vector;
69 component extension_7seg
72 RESET_VALUE : std_logic
76 sys_clk : in std_logic;
77 sys_res_n : in std_logic;
78 -- general extension interface
79 ext_reg : in extmod_rec;
80 -- data_out : out gp_register_t;
82 -- val : in std_logic_vector(4 downto 0);
83 -- pos : in std_logic_vector(1 downto 0);
86 o_digit0 : out std_logic_vector(0 to 6);
87 o_digit1 : out std_logic_vector(0 to 6);
88 o_digit2 : out std_logic_vector(0 to 6);
89 o_digit3 : out std_logic_vector(0 to 6)
91 end component extension_7seg;
93 end extension_7seg_pkg;
95 package body extension_7seg_pkg is
97 function digit_decode(value : sseg_digit) return std_logic_vector is
101 when "00000" => return DIGIT_0;
102 when "00001" => return DIGIT_1;
103 when "00010" => return DIGIT_2;
104 when "00011" => return DIGIT_3;
105 when "00100" => return DIGIT_4;
106 when "00101" => return DIGIT_5;
107 when "00110" => return DIGIT_6;
108 when "00111" => return DIGIT_7;
109 when "01000" => return DIGIT_8;
110 when "01001" => return DIGIT_9;
111 when "01010" => return DIGIT_A;
112 when "01011" => return DIGIT_B;
113 when "01100" => return DIGIT_C;
114 when "01101" => return DIGIT_D;
115 when "01110" => return DIGIT_E;
116 when "01111" => return DIGIT_F;
117 when "10000" => return "1111111";
118 --when "11111" => return DIGIT_MINUS;
119 when OTHERS => return DIGIT_CLEAR;
122 end function digit_decode;
124 end extension_7seg_pkg;