cpu/src/extension_7seg_b.vhd

   1 library IEEE;\r
   2 use IEEE.std_logic_1164.all;\r
   3 use IEEE.numeric_std.all;\r
   4 \r
   5 --use work.math_pkg.all;\r
   6 use work.common_pkg.all;\r
   7 use work.core_pkg.all;\r
   8 \r
   9 use work.mem_pkg.all;\r
  10 use work.extension_pkg.all;\r
  11 use work.extension_7seg_pkg.all;\r
  12 \r
  13 architecture behav of extension_7seg is\r
  14 \r
  15 signal s_state, s_state_nxt : sseg_state_rec;\r
  16 signal ext_reg_r  : extmod_rec;\r
  17 \r
  18 begin\r
  19 \r
  20 seg_syn: process(sys_clk, sys_res_n)\r
  21 \r
  22 begin\r
  23 \r
  24         if (sys_res_n = RESET_VALUE) then\r
  25                 \r
  26                 s_state.digit0 <= (others => '0');--set(0,7);\r
  27                 s_state.digit1 <= (others => '0');--set(0,7);\r
  28                 s_state.digit2 <= (others => '0');--set(0,7);\r
  29                 s_state.digit3 <= (others => '0');--set(0,7);\r
  30 \r
  31                 ext_reg_r.sel <='0';\r
  32                 ext_reg_r.wr_en <= '0';\r
  33                 ext_reg_r.byte_en <= (others => '0');\r
  34                 ext_reg_r.data <= (others => '0');\r
  35                 ext_reg_r.addr <= (others => '0');\r
  36                 \r
  37         elsif rising_edge(sys_clk) then\r
  38                 \r
  39                 s_state <= s_state_nxt;\r
  40                 ext_reg_r <= ext_reg;\r
  41                 \r
  42         end if;\r
  43         \r
  44 end process; \r
  45 \r
  46 seg_asyn: process(s_state, ext_reg_r)   \r
  47 \r
  48 begin\r
  49         s_state_nxt <= s_state; \r
  50 \r
  51         if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then\r
  52 \r
  53 \r
  54                 case ext_reg_r.byte_en(1 downto 0) is\r
  55                 when "00" => null;\r
  56                         s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));\r
  57                         s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));\r
  58                         s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));\r
  59                         s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));\r
  60                 when others => \r
  61                         s_state_nxt.digit0 <= (others => '1');\r
  62                         s_state_nxt.digit1 <= (others => '1');\r
  63                         s_state_nxt.digit2 <= (others => '1');\r
  64                         s_state_nxt.digit3 <= (others => '1');\r
  65                 end case;\r
  66 \r
  67 \r
  68         end if;\r
  69 \r
  70 end process; --ps2_next\r
  71 \r
  72 seg_out: process(s_state)\r
  73 begin\r
  74         \r
  75         o_digit0 <= not(s_state.digit0);\r
  76         o_digit1 <= not(s_state.digit1);\r
  77         o_digit2 <= not(s_state.digit2);\r
  78         o_digit3 <= not(s_state.digit3);\r
  79 \r
  80 end process;\r
  81 \r
  82 end behav;\r