cpu/src/extension_7seg_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 --use work.math_pkg.all;
   6 use work.common_pkg.all;
   7 use work.core_pkg.all;
   8
   9 use work.mem_pkg.all;
  10 use work.extension_pkg.all;
  11 use work.extension_7seg_pkg.all;
  12
  13 architecture behav of extension_7seg is
  14
  15 signal s_state, s_state_nxt : sseg_state_rec;
  16 signal ext_reg_r  : extmod_rec;
  17
  18 begin
  19
  20 seg_syn: process(sys_clk, sys_res_n)
  21
  22 begin
  23
  24         if (sys_res_n = RESET_VALUE) then
  25
  26                 s_state.digit0 <= (others => '0');--set(0,7);
  27                 s_state.digit1 <= (others => '0');--set(0,7);
  28                 s_state.digit2 <= (others => '0');--set(0,7);
  29                 s_state.digit3 <= (others => '0');--set(0,7);
  30
  31                 ext_reg_r.sel <='0';
  32                 ext_reg_r.wr_en <= '0';
  33                 ext_reg_r.byte_en <= (others => '0');
  34                 ext_reg_r.data <= (others => '0');
  35                 ext_reg_r.addr <= (others => '0');
  36
  37         elsif rising_edge(sys_clk) then
  38
  39                 s_state <= s_state_nxt;
  40                 ext_reg_r <= ext_reg;
  41
  42         end if;
  43
  44 end process;
  45
  46 seg_asyn: process(s_state, ext_reg_r)
  47
  48 begin
  49         s_state_nxt <= s_state;
  50
  51         if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
  52
  53
  54 --              case ext_reg_r.byte_en(1 downto 0) is
  55 --              when "00" => null;
  56 --                      s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
  57 --                      s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
  58 --                      s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
  59 --                      s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
  60 --              when others =>
  61 --                      s_state_nxt.digit0 <= (others => '1');
  62 --                      s_state_nxt.digit1 <= (others => '1');
  63 --                      s_state_nxt.digit2 <= (others => '1');
  64 --                      s_state_nxt.digit3 <= (others => '1');
  65 --              end case;
  66
  67                 if (ext_reg_r.byte_en(0) = '1') then
  68                         s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
  69                         s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
  70                 end if;
  71                 if (ext_reg_r.byte_en(1) = '1') then
  72                         s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
  73                         s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
  74                 end if;
  75
  76         end if;
  77
  78 end process; --ps2_next
  79
  80 seg_out: process(s_state)
  81 begin
  82
  83         o_digit0 <= not(s_state.digit0);
  84         o_digit1 <= not(s_state.digit1);
  85         o_digit2 <= not(s_state.digit2);
  86         o_digit3 <= not(s_state.digit3);
  87
  88 end process;
  89
  90 end behav;