cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7 use work.gpm_pkg.all;
   8
   9 architecture behav of execute_stage is
  10
  11 signal condition : condition_t;
  12 signal op_group : op_info_t;
  13 signal op_detail : op_opt_t;
  14 signal left_operand, right_operand : gp_register_t;
  15 signal alu_state, alu_nxt : alu_result_rec;
  16 signal psw : status_rec;
  17
  18 type exec_internal is record
  19         result : gp_register_t;
  20         res_addr : gp_addr_t;
  21         alu_jump : std_logic;
  22         brpr    : std_logic;
  23         wr_en   : std_logic;
  24 end record;
  25
  26 signal reg, reg_nxt : exec_internal;
  27
  28 begin
  29
  30 alu_inst : alu
  31 port map(clk, reset, condition, op_group,
  32          left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
  33
  34 gpm_inst : gpm
  35         generic map(RESET_VALUE)
  36         port map(clk,reset,alu_nxt,psw);
  37
  38 syn: process(clk, reset)
  39
  40 begin
  41
  42         if reset = RESET_VALUE then
  43                 reg.alu_jump <= '0';
  44                 reg.brpr <= '0';
  45                 reg.wr_en <= '0';
  46                 reg.result <= (others =>'0');
  47                 reg.res_addr <= (others => '0');
  48         elsif rising_edge(clk) then
  49                 reg <= reg_nxt;
  50         end if;
  51
  52 end process;
  53
  54 asyn: process(reset,dec_instr, alu_nxt, psw, reg)
  55 begin
  56
  57         condition <= dec_instr.condition;
  58         op_group <= dec_instr.op_group;
  59         op_detail <= dec_instr.op_detail;
  60         left_operand <= dec_instr.src1;
  61         right_operand <= dec_instr.src2;
  62
  63
  64         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0');
  65
  66
  67         if reset = RESET_VALUE then
  68                 condition <= COND_NEVER;
  69         else
  70
  71         end if;
  72
  73         reg_nxt.brpr <= alu_nxt.brpr;
  74         reg_nxt.alu_jump <= alu_nxt.alu_jump;
  75         reg_nxt.wr_en <= alu_nxt.reg_op;
  76         reg_nxt.result <= alu_nxt.result;
  77         reg_nxt.res_addr <= alu_nxt.result_addr;
  78
  79 end process asyn;
  80
  81 result <= reg.result;
  82 result_addr <= reg.res_addr;
  83 alu_jump <= reg.alu_jump;
  84 brpr <= reg.brpr;
  85 wr_en <= reg.wr_en;
  86 dmem <= alu_nxt.mem_op;
  87 dmem_write_en <= alu_nxt.mem_en;
  88 hword <= alu_nxt.hw_op;
  89 byte_s <= alu_nxt.byte_op;
  90
  91 end behav;
  92