cpu/src/exec_op/shift_op_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7
   8 architecture shift_op of exec_op is
   9
  10         signal arith, rs, carry : std_logic;
  11
  12 begin
  13
  14         arith <=  op_detail(ARITH_OPT);
  15         rs      <=  op_detail(RIGHT_OPT);
  16         carry <= op_detail(CARRY_OPT);
  17
  18 calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
  19                 variable alu_result_v : alu_result_rec;
  20                 variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
  21                 variable tmp_sb : std_logic;
  22 begin
  23                 alu_result_v := alu_state;
  24
  25                 if rs = '1' then
  26                         tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
  27                         tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
  28                         tmp_shift := tmp_shift sra to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
  29
  30                         alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
  31                 else
  32                         tmp_sb := (carry and alu_state.status.carry and not(arith));
  33                         tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
  34                         tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
  35
  36                         alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
  37                 end if;
  38
  39                 alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);
  40
  41                 alu_result <= alu_result_v;
  42
  43 end process;
  44
  45 end architecture shift_op;