cpu/src/exec_op/add_op_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7
   8 architecture add_op of exec_op is
   9
  10 signal sub, addc : std_logic;
  11
  12 begin
  13
  14 sub <= op_detail(SUB_OPT);
  15 addc <= op_detail(CARRY_OPT);
  16
  17 calc: process(left_operand, right_operand, alu_state, sub, addc)
  18         variable alu_result_v : alu_result_rec;
  19         variable complement             : gp_register_t;
  20         variable carry_res              : unsigned(gp_register_t'length downto 0);
  21         variable tmp_right_operand : unsigned(gp_register_t'length downto 0);
  22         variable oflo1, oflo2, l_neg, r_neg : std_logic;
  23         variable addcarry               : unsigned(carry_res'range);
  24 begin
  25                 alu_result_v := alu_state;
  26                 addcarry := (others => '0');
  27                 addcarry(0):= (alu_state.status.carry and addc) or (sub and not(addc));
  28                 if sub = '1' then
  29                         carry_res := unsigned('0' & left_operand)+unsigned('0' & not(right_operand))+addcarry;
  30                 else
  31                         carry_res := unsigned('0' & left_operand)+unsigned('0' & right_operand)+addcarry;
  32                 end if;
  33                 alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
  34                 alu_result_v.status.carry := carry_res(carry_res'high);
  35                 alu_result_v.status.oflo := add_oflo(left_operand(gp_register_t'high),right_operand(gp_register_t'high) xor sub, carry_res(gp_register_t'high));
  36                 -- addcarry := (others =>'0');
  37                 -- addcarry(0) := alu_state.status.carry and addc;
  38
  39                 -- complement := inc(not(right_operand));
  40                 -- l_neg := left_operand(gp_register_t'high);
  41
  42                 -- carry_res := unsigned('0' & left_operand)+addcarry;
  43                 -- oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
  44
  45                 -- if sub = '1' then
  46                         -- tmp_right_operand := unsigned('0' & complement);
  47                 -- else
  48                         -- tmp_right_operand := unsigned('0' & right_operand);
  49                 -- end if;
  50
  51                 -- l_neg := carry_res(gp_register_t'high);
  52                 -- r_neg := tmp_right_operand(gp_register_t'high);
  53
  54                 -- carry_res := carry_res + tmp_right_operand;
  55                 -- oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
  56
  57
  58                 -- alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
  59                 -- alu_result_v.status.carry := carry_res(carry_res'high);
  60         -- --   alu_result_v.result := (0 => '1', others => '0');
  61
  62                 -- alu_result_v.status.oflo := oflo1 or oflo2;
  63
  64                 -- --sign will be set globally.
  65                 -- --zero will be set globally.
  66
  67                 alu_result <= alu_result_v;
  68 end process;
  69
  70 end architecture add_op;