48761ea0336ba0316dca0d0f4d8477e1550c8da9
[calu.git] / cpu / src / decode_stage_b.vhd
1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4
5 use work.core_pkg.all;
6 use work.common_pkg.all;
7
8 architecture behav of decode_stage is
9
10
11 begin
12
13 syn: process(sys_clk, reset)
14
15 begin
16
17         if (reset = RESET_VALUE) then
18                                 
19         elsif rising_edge(sys_clk) then
20                 
21         end if;
22         
23 end process; 
24
25 end behav;
26