cpu/src/decode_stage.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7
   8 entity decode_stage is
   9
  10         generic (
  11                         -- active reset value
  12                         RESET_VALUE : std_logic;
  13                         -- active logic value
  14                         LOGIC_ACT : std_logic;
  15
  16                         );
  17         port(
  18                 --System inputs
  19                         clk : in std_logic;
  20                         reset : in std_logic;
  21
  22                 --Data inputs
  23                         instruction : in instruction_word_t;
  24                         reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  25                         reg_wr_data : in gp_register_t;
  26                         reg_we : in std_logic;
  27
  28                 --Data outputs
  29                         reg1_rd_data : gp_register_t;
  30                         reg2_rd_data : gp_register_t;
  31                         branch_prediction_res : instruction_word_t;
  32                         branch_prediction_bit : std_logic
  33
  34                 );
  35
  36 end decode_stage;