cpu/src/decode_stage.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7
   8
   9 entity decode_stage is
  10
  11         generic (
  12                         -- active reset value
  13                         RESET_VALUE : std_logic;
  14                         -- active logic value
  15                         LOGIC_ACT : std_logic
  16
  17                         );
  18         port(
  19                 --System inputs
  20                         clk : in std_logic;
  21                         reset : in std_logic;
  22
  23                 --Data inputs
  24                         instruction : in instruction_word_t;
  25                         reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  26                         reg_wr_data : in gp_register_t;
  27                         reg_we : in std_logic;
  28
  29                 --Data outputs
  30                         reg1_rd_data : out gp_register_t;
  31                         reg2_rd_data : out gp_register_t;
  32                         branch_prediction_res : out instruction_word_t;
  33                         branch_prediction_bit : out std_logic
  34
  35                 );
  36
  37 end decode_stage;
  38
  39