1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
27 use work.core_pkg.all;
28 use work.extension_pkg.all;
34 sys_res : in std_logic;
35 soft_res : in std_logic;
36 sys_clk : in std_logic;
37 -- result : out gp_register_t;
38 -- reg_wr_data : out gp_register_t
40 bus_tx : out std_logic;
41 bus_rx : in std_logic;
45 sseg0 : out std_logic_vector(0 to 6);
46 sseg1 : out std_logic_vector(0 to 6);
47 sseg2 : out std_logic_vector(0 to 6);
48 sseg3 : out std_logic_vector(0 to 6)
53 architecture behav of core_top is
55 constant SYNC_STAGES : integer := 2;
56 constant RESET_VALUE : std_logic := '0';
58 signal jump_result : instruction_addr_t;
59 signal jump_result_pin : instruction_addr_t;
60 signal prediction_result_pin : instruction_addr_t;
61 signal branch_prediction_bit_pin : std_logic;
62 signal alu_jump_bit_pin : std_logic;
63 signal instruction_pin : instruction_word_t;
64 signal prog_cnt_pin : instruction_addr_t;
66 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
67 signal reg_wr_data_pin : gp_register_t;
68 signal reg_we_pin : std_logic;
69 signal to_next_stage : dec_op;
71 -- signal reg1_rd_data_pin : gp_register_t;
72 -- signal reg2_rd_data_pin : gp_register_t;
74 signal result_pin : gp_register_t;--reg
75 signal result_addr_pin : gp_addr_t;--reg
76 signal addr_pin : word_t; --memaddr
77 signal data_pin : gp_register_t; --mem data --ureg
78 signal alu_jump_pin : std_logic;--reg
79 signal brpr_pin : std_logic; --reg
80 signal wr_en_pin : std_logic;--regop --reg
81 signal dmem_pin : std_logic;--memop
82 signal dmem_wr_en_pin : std_logic;
83 signal hword_pin : std_logic;
84 signal byte_s_pin : std_logic;
86 signal gpm_in_pin : extmod_rec;
87 signal gpm_out_pin : gp_register_t;
88 signal nop_pin : std_logic;
90 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
91 signal sys_res_n, soft_res_n : std_logic;
92 signal xilinxfail : std_logic;
94 signal int_req : interrupt_t;
96 signal new_im_data : std_logic;
97 signal im_addr, im_data : gp_register_t;
99 signal vers, vers_nxt : exec2wb_rec;
102 fetch_st : fetch_stage
111 clk => sys_clk, --: in std_logic;
112 reset => sys_res_n, --: in std_logic;
113 s_reset => soft_res_n,
115 jump_result => jump_result_pin, --: in instruction_addr_t;
116 prediction_result => prediction_result_pin, --: in instruction_addr_t;
117 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
118 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
120 -- instruction memory program port :D
121 new_im_data_in => new_im_data,
125 instruction => instruction_pin, --: out instruction_word_t
126 prog_cnt => prog_cnt_pin,
130 decode_st : decode_stage
132 -- active reset value
134 -- active logic value
140 clk => sys_clk, --: in std_logic;
141 reset => xilinxfail, -- : in std_logic;
144 instruction => instruction_pin, --: in instruction_word_t;
145 prog_cnt => prog_cnt_pin,
146 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
147 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
148 reg_we => reg_we_pin, --: in std_logic;
152 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
153 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
154 to_next_stage => to_next_stage
157 exec_st : execute_stage
159 port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
160 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
163 vers_nxt.result <= result_pin;
164 vers_nxt.result_addr <= result_addr_pin;
165 vers_nxt.address <= addr_pin;
166 vers_nxt.ram_data <= data_pin;
167 vers_nxt.alu_jmp <= alu_jump_pin;
168 vers_nxt.br_pred <= brpr_pin;
169 vers_nxt.write_en <= wr_en_pin;
170 vers_nxt.dmem_en <= dmem_pin;
171 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
172 vers_nxt.hword <= hword_pin;
173 vers_nxt.byte_s <= byte_s_pin;
175 -- writeback_st : writeback_stage
176 -- generic map('0', '1')
177 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
178 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
179 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
182 writeback_st : writeback_stage
183 generic map('0', '1', "s3e", 434)
184 port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
185 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
186 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
187 -- instruction memory program port :D
188 new_im_data, im_addr, im_data,
189 -- sseg0, sseg1, sseg2, sseg3,
193 syn: process(sys_clk, sys_res)
197 if sys_res = '1' then
199 -- vers.result <= (others => '0');
200 -- vers.result_addr <= (others => '0');
201 -- vers.address <= (others => '0');
202 -- vers.ram_data <= (others => '0');
203 -- vers.alu_jmp <= '0';
204 -- vers.br_pred <= '0';
205 -- vers.write_en <= '0';
206 -- vers.dmem_en <= '0';
207 -- vers.dmem_write_en <= '0';
208 -- vers.hword <= '0';
209 -- vers.byte_s <= '0';
211 sync <= (others => '0');
212 sync2 <= (others => '0');
214 elsif rising_edge(sys_clk) then
217 sync(1) <= not sys_res;
218 for i in 2 to SYNC_STAGES loop
219 sync(i) <= sync(i - 1);
221 sync2(1) <= not soft_res;
222 for i in 2 to SYNC_STAGES loop
223 sync2(i) <= sync2(i - 1);
229 sys_res_n <= sync(SYNC_STAGES);
230 soft_res_n <= sync2(SYNC_STAGES);
231 xilinxfail <= sys_res_n and soft_res_n;
233 --init : process(all)
236 -- jump_result_pin <= (others => '0');
237 -- alu_jump_bit_pin <= '0';
238 -- reg_w_addr_pin <= (others => '0');
239 -- reg_wr_data_pin <= (others => '0');
240 -- reg_we_pin <= '0';
244 -- result <= result_pin;
245 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
247 jump_result <= prog_cnt_pin; --jump_result_pin;
250 -- reg_wr_data <= reg_wr_data_pin;