2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 soft_res : in std_logic;
15 sys_clk : in std_logic;
16 -- result : out gp_register_t;
17 -- reg_wr_data : out gp_register_t
19 bus_tx : out std_logic;
20 bus_rx : in std_logic;
23 -- RW, EN, RS, DB7, DB6, DB5, DB4
24 lcd_data : out std_logic_vector(6 downto 0)
29 architecture behav of core_top is
31 constant SYNC_STAGES : integer := 2;
32 constant RESET_VALUE : std_logic := '0';
34 signal jump_result : instruction_addr_t;
35 signal jump_result_pin : instruction_addr_t;
36 signal prediction_result_pin : instruction_addr_t;
37 signal branch_prediction_bit_pin : std_logic;
38 signal alu_jump_bit_pin : std_logic;
39 signal instruction_pin : instruction_word_t;
40 signal prog_cnt_pin : instruction_addr_t;
42 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
43 signal reg_wr_data_pin : gp_register_t;
44 signal reg_we_pin : std_logic;
45 signal to_next_stage : dec_op;
47 -- signal reg1_rd_data_pin : gp_register_t;
48 -- signal reg2_rd_data_pin : gp_register_t;
50 signal result_pin : gp_register_t;--reg
51 signal result_addr_pin : gp_addr_t;--reg
52 signal addr_pin : word_t; --memaddr
53 signal data_pin : gp_register_t; --mem data --ureg
54 signal alu_jump_pin : std_logic;--reg
55 signal brpr_pin : std_logic; --reg
56 signal wr_en_pin : std_logic;--regop --reg
57 signal dmem_pin : std_logic;--memop
58 signal dmem_wr_en_pin : std_logic;
59 signal hword_pin : std_logic;
60 signal byte_s_pin : std_logic;
62 signal gpm_in_pin : extmod_rec;
63 signal gpm_out_pin : gp_register_t;
64 signal nop_pin : std_logic;
66 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
67 signal sys_res_n, soft_res_n : std_logic;
68 signal xilinxfail : std_logic;
70 signal int_req : interrupt_t;
72 signal new_im_data : std_logic;
73 signal im_addr, im_data : gp_register_t;
75 signal vers, vers_nxt : exec2wb_rec;
78 fetch_st : fetch_stage
87 clk => sys_clk, --: in std_logic;
88 reset => sys_res_n, --: in std_logic;
89 s_reset => soft_res_n,
91 jump_result => jump_result_pin, --: in instruction_addr_t;
92 prediction_result => prediction_result_pin, --: in instruction_addr_t;
93 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
94 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
96 -- instruction memory program port :D
97 new_im_data_in => new_im_data,
101 instruction => instruction_pin, --: out instruction_word_t
102 prog_cnt => prog_cnt_pin,
106 decode_st : decode_stage
108 -- active reset value
110 -- active logic value
116 clk => sys_clk, --: in std_logic;
117 reset => xilinxfail, -- : in std_logic;
120 instruction => instruction_pin, --: in instruction_word_t;
121 prog_cnt => prog_cnt_pin,
122 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
123 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
124 reg_we => reg_we_pin, --: in std_logic;
128 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
129 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
130 to_next_stage => to_next_stage
133 exec_st : execute_stage
135 port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
136 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
139 vers_nxt.result <= result_pin;
140 vers_nxt.result_addr <= result_addr_pin;
141 vers_nxt.address <= addr_pin;
142 vers_nxt.ram_data <= data_pin;
143 vers_nxt.alu_jmp <= alu_jump_pin;
144 vers_nxt.br_pred <= brpr_pin;
145 vers_nxt.write_en <= wr_en_pin;
146 vers_nxt.dmem_en <= dmem_pin;
147 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
148 vers_nxt.hword <= hword_pin;
149 vers_nxt.byte_s <= byte_s_pin;
151 -- writeback_st : writeback_stage
152 -- generic map('0', '1')
153 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
154 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
155 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
158 writeback_st : writeback_stage
159 generic map('0', '1', "s3e", 434)
160 port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
161 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
162 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
163 -- instruction memory program port :D
164 new_im_data, im_addr, im_data,
165 open, open, open, open, int_req, lcd_data);
168 syn: process(sys_clk, sys_res)
172 if sys_res = '1' then
174 -- vers.result <= (others => '0');
175 -- vers.result_addr <= (others => '0');
176 -- vers.address <= (others => '0');
177 -- vers.ram_data <= (others => '0');
178 -- vers.alu_jmp <= '0';
179 -- vers.br_pred <= '0';
180 -- vers.write_en <= '0';
181 -- vers.dmem_en <= '0';
182 -- vers.dmem_write_en <= '0';
183 -- vers.hword <= '0';
184 -- vers.byte_s <= '0';
186 sync <= (others => '0');
187 sync2 <= (others => '0');
189 elsif rising_edge(sys_clk) then
192 sync(1) <= not sys_res;
193 for i in 2 to SYNC_STAGES loop
194 sync(i) <= sync(i - 1);
196 sync2(1) <= not soft_res;
197 for i in 2 to SYNC_STAGES loop
198 sync2(i) <= sync2(i - 1);
204 sys_res_n <= sync(SYNC_STAGES);
205 soft_res_n <= sync2(SYNC_STAGES);
206 xilinxfail <= sys_res_n and soft_res_n;
208 --init : process(all)
211 -- jump_result_pin <= (others => '0');
212 -- alu_jump_bit_pin <= '0';
213 -- reg_w_addr_pin <= (others => '0');
214 -- reg_wr_data_pin <= (others => '0');
215 -- reg_we_pin <= '0';
219 -- result <= result_pin;
220 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
222 jump_result <= prog_cnt_pin; --jump_result_pin;
225 -- reg_wr_data <= reg_wr_data_pin;