2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
12 sys_clk : in std_logic;
13 sys_res : in std_logic;
14 result : out gp_register_t;
15 jump_result : out instruction_addr_t;
16 reg_wr_data : out gp_register_t
22 architecture behav of core_top is
24 signal jump_result_pin : instruction_addr_t;
25 signal prediction_result_pin : instruction_addr_t;
26 signal branch_prediction_bit_pin : std_logic;
27 signal alu_jump_bit_pin : std_logic;
28 signal instruction_pin : instruction_word_t;
29 signal prog_cnt_pin : instruction_addr_t;
31 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
32 signal reg_wr_data_pin : gp_register_t;
33 signal reg_we_pin : std_logic;
34 signal to_next_stage : dec_op;
36 -- signal reg1_rd_data_pin : gp_register_t;
37 -- signal reg2_rd_data_pin : gp_register_t;
39 signal result_pin : gp_register_t;--reg
40 signal result_addr_pin : gp_addr_t;--reg
41 signal addr_pin : word_t; --memaddr
42 signal data_pin : gp_register_t; --mem data --ureg
43 signal alu_jump_pin : std_logic;--reg
44 signal brpr_pin : std_logic; --reg
45 signal wr_en_pin : std_logic;--regop --reg
46 signal dmem_pin : std_logic;--memop
47 signal dmem_wr_en_pin : std_logic;
48 signal hword_pin : std_logic;
49 signal byte_s_pin : std_logic;
50 signal nop_pin : std_logic;
56 fetch_st : fetch_stage
65 clk => sys_clk, --: in std_logic;
66 reset => sys_res, --: in std_logic;
69 jump_result => jump_result_pin, --: in instruction_addr_t;
70 prediction_result => prediction_result_pin, --: in instruction_addr_t;
71 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
72 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
75 instruction => instruction_pin, --: out instruction_word_t
76 prog_cnt => prog_cnt_pin
79 decode_st : decode_stage
89 clk => sys_clk, --: in std_logic;
90 reset => sys_res, -- : in std_logic;
93 instruction => instruction_pin, --: in instruction_word_t;
94 prog_cnt => prog_cnt_pin,
95 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
96 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
97 reg_we => reg_we_pin, --: in std_logic;
101 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
102 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
103 to_next_stage => to_next_stage
106 exec_st : execute_stage
108 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
109 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
111 writeback_st : writeback_stage
112 generic map('0', '1')
113 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
114 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
115 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
121 --init : process(all)
124 -- jump_result_pin <= (others => '0');
125 -- alu_jump_bit_pin <= '0';
126 -- reg_w_addr_pin <= (others => '0');
127 -- reg_wr_data_pin <= (others => '0');
128 -- reg_we_pin <= '0';
132 result <= result_pin;
133 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
135 jump_result <= jump_result_pin;
137 reg_wr_data <= reg_wr_data_pin;