2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 soft_res : in std_logic;
15 sys_clk_in : in std_logic;
16 -- result : out gp_register_t;
17 -- reg_wr_data : out gp_register_t
19 bus_tx : out std_logic;
20 bus_rx : in std_logic;
23 sseg0 : out std_logic_vector(0 to 6);
24 sseg1 : out std_logic_vector(0 to 6);
25 sseg2 : out std_logic_vector(0 to 6);
26 sseg3 : out std_logic_vector(0 to 6)
31 architecture behav of core_top is
33 constant SYNC_STAGES : integer := 2;
34 constant RESET_VALUE : std_logic := '0';
36 signal sys_clk : std_logic;
38 signal jump_result : instruction_addr_t;
39 signal jump_result_pin : instruction_addr_t;
40 signal prediction_result_pin : instruction_addr_t;
41 signal branch_prediction_bit_pin : std_logic;
42 signal alu_jump_bit_pin : std_logic;
43 signal instruction_pin : instruction_word_t;
44 signal prog_cnt_pin : instruction_addr_t;
46 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
47 signal reg_wr_data_pin : gp_register_t;
48 signal reg_we_pin : std_logic;
49 signal to_next_stage : dec_op;
51 -- signal reg1_rd_data_pin : gp_register_t;
52 -- signal reg2_rd_data_pin : gp_register_t;
54 signal result_pin : gp_register_t;--reg
55 signal result_addr_pin : gp_addr_t;--reg
56 signal addr_pin : word_t; --memaddr
57 signal data_pin : gp_register_t; --mem data --ureg
58 signal alu_jump_pin : std_logic;--reg
59 signal brpr_pin : std_logic; --reg
60 signal wr_en_pin : std_logic;--regop --reg
61 signal dmem_pin : std_logic;--memop
62 signal dmem_wr_en_pin : std_logic;
63 signal hword_pin : std_logic;
64 signal byte_s_pin : std_logic;
66 signal gpm_in_pin : extmod_rec;
67 signal gpm_out_pin : gp_register_t;
68 signal nop_pin : std_logic;
70 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
71 signal sys_res_n, soft_res_n : std_logic;
73 signal int_req : interrupt_t;
75 signal new_im_data : std_logic;
76 signal im_addr, im_data : gp_register_t;
78 signal vers, vers_nxt : exec2wb_rec;
84 inclk0 : IN STD_LOGIC := '0';
90 pll_inst : pll PORT MAP (
96 fetch_st : fetch_stage
105 clk => sys_clk, --: in std_logic;
106 reset => sys_res_n, --: in std_logic;
107 s_reset => soft_res_n,
109 jump_result => jump_result_pin, --: in instruction_addr_t;
110 prediction_result => prediction_result_pin, --: in instruction_addr_t;
111 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
112 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
114 -- instruction memory program port :D
115 new_im_data_in => new_im_data,
119 instruction => instruction_pin, --: out instruction_word_t
120 prog_cnt => prog_cnt_pin,
124 decode_st : decode_stage
126 -- active reset value
128 -- active logic value
134 clk => sys_clk, --: in std_logic;
135 reset => sys_res_n and soft_res_n, -- : in std_logic;
138 instruction => instruction_pin, --: in instruction_word_t;
139 prog_cnt => prog_cnt_pin,
140 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
141 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
142 reg_we => reg_we_pin, --: in std_logic;
146 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
147 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
148 to_next_stage => to_next_stage
151 exec_st : execute_stage
153 port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
154 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
157 vers_nxt.result <= result_pin;
158 vers_nxt.result_addr <= result_addr_pin;
159 vers_nxt.address <= addr_pin;
160 vers_nxt.ram_data <= data_pin;
161 vers_nxt.alu_jmp <= alu_jump_pin;
162 vers_nxt.br_pred <= brpr_pin;
163 vers_nxt.write_en <= wr_en_pin;
164 vers_nxt.dmem_en <= dmem_pin;
165 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
166 vers_nxt.hword <= hword_pin;
167 vers_nxt.byte_s <= byte_s_pin;
169 -- writeback_st : writeback_stage
170 -- generic map('0', '1')
171 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
172 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
173 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
176 writeback_st : writeback_stage
177 generic map('0', '1', "altera", 2083)
178 port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
179 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
180 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
181 -- instruction memory program port :D
182 new_im_data, im_addr, im_data,
183 sseg0, sseg1, sseg2, sseg3, int_req);
186 syn: process(sys_clk, sys_res, soft_res)
190 if sys_res = '1' then
191 -- vers.result <= (others => '0');
192 -- vers.result_addr <= (others => '0');
193 -- vers.address <= (others => '0');
194 -- vers.ram_data <= (others => '0');
195 -- vers.alu_jmp <= '0';
196 -- vers.br_pred <= '0';
197 -- vers.write_en <= '0';
198 -- vers.dmem_en <= '0';
199 -- vers.dmem_write_en <= '0';
200 -- vers.hword <= '0';
201 -- vers.byte_s <= '0';
203 sync <= (others => '0');
204 sync2 <= (others => '0');
206 elsif rising_edge(sys_clk) then
208 sync(1) <= not sys_res;
209 for i in 2 to SYNC_STAGES loop
210 sync(i) <= sync(i - 1);
212 sync2(1) <= not soft_res;
213 for i in 2 to SYNC_STAGES loop
214 sync2(i) <= sync2(i - 1);
221 sys_res_n <= sync(SYNC_STAGES);
222 soft_res_n <= sync2(SYNC_STAGES);
224 --init : process(all)
227 -- jump_result_pin <= (others => '0');
228 -- alu_jump_bit_pin <= '0';
229 -- reg_w_addr_pin <= (others => '0');
230 -- reg_wr_data_pin <= (others => '0');
231 -- reg_we_pin <= '0';
235 -- result <= result_pin;
236 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
238 jump_result <= prog_cnt_pin; --jump_result_pin;
241 -- reg_wr_data <= reg_wr_data_pin;