cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top is
  10
  11         port(
  12                 --System input pins
  13                    sys_res : in std_logic;
  14                         sys_clk : in std_logic;
  15 --                      result : out gp_register_t;
  16 --                      reg_wr_data : out gp_register_t
  17                   -- uart
  18                         bus_tx : out std_logic;
  19                         bus_rx : in std_logic;
  20
  21                         sseg0 : out std_logic_vector(0 to 6);
  22                         sseg1 : out std_logic_vector(0 to 6);
  23                         sseg2 : out std_logic_vector(0 to 6);
  24                         sseg3 : out std_logic_vector(0 to 6)
  25                 );
  26
  27 end core_top;
  28
  29 architecture behav of core_top is
  30
  31                 constant SYNC_STAGES : integer := 2;
  32                 constant RESET_VALUE : std_logic := '0';
  33
  34                 signal jump_result : instruction_addr_t;
  35                 signal jump_result_pin : instruction_addr_t;
  36                 signal prediction_result_pin : instruction_addr_t;
  37                 signal branch_prediction_bit_pin : std_logic;
  38                 signal alu_jump_bit_pin : std_logic;
  39                 signal instruction_pin : instruction_word_t;
  40                 signal prog_cnt_pin : instruction_addr_t;
  41
  42                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  43                 signal reg_wr_data_pin : gp_register_t;
  44                 signal reg_we_pin : std_logic;
  45                 signal to_next_stage : dec_op;
  46
  47 --              signal reg1_rd_data_pin : gp_register_t;
  48 --              signal reg2_rd_data_pin : gp_register_t;
  49
  50                  signal result_pin : gp_register_t;--reg
  51                  signal result_addr_pin : gp_addr_t;--reg
  52                  signal addr_pin : word_t; --memaddr
  53                  signal data_pin : gp_register_t; --mem data --ureg
  54                  signal alu_jump_pin : std_logic;--reg
  55                  signal brpr_pin  : std_logic;  --reg
  56                  signal wr_en_pin : std_logic;--regop --reg
  57                  signal dmem_pin  : std_logic;--memop
  58                  signal dmem_wr_en_pin : std_logic;
  59                  signal hword_pin  : std_logic;
  60                  signal byte_s_pin : std_logic;
  61
  62                  signal gpm_in_pin : extmod_rec;
  63                  signal gpm_out_pin : gp_register_t;
  64                  signal nop_pin : std_logic;
  65
  66                  signal sync : std_logic_vector(1 to SYNC_STAGES);
  67                  signal sys_res_n : std_logic;
  68
  69                  signal vers, vers_nxt : exec2wb_rec;
  70 begin
  71
  72         fetch_st : fetch_stage
  73                 generic map (
  74
  75                         '0',
  76                         '1'
  77                 )
  78
  79                 port map (
  80                 --System inputs
  81                         clk => sys_clk, --: in std_logic;
  82                         reset => sys_res_n, --: in std_logic;
  83
  84                 --Data inputs
  85                         jump_result => jump_result_pin, --: in instruction_addr_t;
  86                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  87                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  88                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  89
  90                 --Data outputs
  91                         instruction => instruction_pin, --: out instruction_word_t
  92                         prog_cnt => prog_cnt_pin
  93                 );
  94
  95         decode_st : decode_stage
  96                 generic map (
  97                         -- active reset value
  98                         '0',
  99                         -- active logic value
 100                         '1'
 101
 102                         )
 103                 port map (
 104                 --System inputs
 105                         clk => sys_clk, --: in std_logic;
 106                         reset => sys_res_n, -- : in std_logic;
 107
 108                 --Data inputs
 109                         instruction => instruction_pin, --: in instruction_word_t;
 110                         prog_cnt => prog_cnt_pin,
 111                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 112                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 113                         reg_we => reg_we_pin, --: in std_logic;
 114                         nop => nop_pin,
 115
 116                 --Data outputs
 117                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 118                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 119                         to_next_stage => to_next_stage
 120                 );
 121
 122           exec_st : execute_stage
 123                 generic map('0')
 124                 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 125                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 126
 127
 128                         vers_nxt.result <= result_pin;
 129                         vers_nxt.result_addr <= result_addr_pin;
 130                         vers_nxt.address <= addr_pin;
 131                         vers_nxt.ram_data <= data_pin;
 132                         vers_nxt.alu_jmp <= alu_jump_pin;
 133                         vers_nxt.br_pred <= brpr_pin;
 134                         vers_nxt.write_en <= wr_en_pin;
 135                         vers_nxt.dmem_en <= dmem_pin;
 136                         vers_nxt.dmem_write_en <= dmem_wr_en_pin;
 137                         vers_nxt.hword <= hword_pin;
 138                         vers_nxt.byte_s <= byte_s_pin;
 139
 140 --          writeback_st : writeback_stage
 141 --                generic map('0', '1')
 142 --                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 143 --                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 144 --                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 145 --
 146
 147                         writeback_st : writeback_stage
 148                 generic map('0', '1')
 149                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
 150                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
 151                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
 152
 153
 154 syn: process(sys_clk, sys_res)
 155
 156 begin
 157
 158         if sys_res = '0' then
 159 --                      vers.result <= (others => '0');
 160 --                      vers.result_addr <= (others => '0');
 161 --                      vers.address <= (others => '0');
 162 --                      vers.ram_data <= (others => '0');
 163 --                      vers.alu_jmp <= '0';
 164 --                      vers.br_pred <= '0';
 165 --                      vers.write_en <= '0';
 166 --                      vers.dmem_en <= '0';
 167 --                      vers.dmem_write_en <= '0';
 168 --                      vers.hword <= '0';
 169 --                      vers.byte_s <= '0';
 170
 171                 sync <= (others => '0');
 172
 173         elsif rising_edge(sys_clk) then
 174 --              vers <= vers_nxt;
 175                         sync(1) <= sys_res;
 176                         for i in 2 to SYNC_STAGES loop
 177                                 sync(i) <= sync(i - 1);
 178                         end loop;
 179
 180         end if;
 181
 182 end process;
 183
 184 sys_res_n <= sync(SYNC_STAGES);
 185
 186 --init : process(all)
 187
 188 --begin
 189 --      jump_result_pin <= (others => '0');
 190 --      alu_jump_bit_pin <= '0';
 191 --      reg_w_addr_pin <= (others => '0');
 192 --      reg_wr_data_pin <= (others => '0');
 193 --      reg_we_pin <= '0';
 194
 195 --end process;
 196
 197 --      result <= result_pin;
 198         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 199
 200         jump_result <= prog_cnt_pin; --jump_result_pin;
 201 --      sys_res <= '1';
 202
 203 --      reg_wr_data <= reg_wr_data_pin;
 204
 205 end behav;