2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_clk : in std_logic;
14 sys_res : in std_logic;
15 result : out gp_register_t;
16 jump_result : out instruction_addr_t;
17 reg_wr_data : out gp_register_t
23 architecture behav of core_top is
25 signal jump_result_pin : instruction_addr_t;
26 signal prediction_result_pin : instruction_addr_t;
27 signal branch_prediction_bit_pin : std_logic;
28 signal alu_jump_bit_pin : std_logic;
29 signal instruction_pin : instruction_word_t;
30 signal prog_cnt_pin : instruction_addr_t;
32 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
33 signal reg_wr_data_pin : gp_register_t;
34 signal reg_we_pin : std_logic;
35 signal to_next_stage : dec_op;
37 -- signal reg1_rd_data_pin : gp_register_t;
38 -- signal reg2_rd_data_pin : gp_register_t;
40 signal result_pin : gp_register_t;--reg
41 signal result_addr_pin : gp_addr_t;--reg
42 signal addr_pin : word_t; --memaddr
43 signal data_pin : gp_register_t; --mem data --ureg
44 signal alu_jump_pin : std_logic;--reg
45 signal brpr_pin : std_logic; --reg
46 signal wr_en_pin : std_logic;--regop --reg
47 signal dmem_pin : std_logic;--memop
48 signal dmem_wr_en_pin : std_logic;
49 signal hword_pin : std_logic;
50 signal byte_s_pin : std_logic;
52 signal gpm_in_pin : extmod_rec;
53 signal gpm_out_pin : gp_register_t;
54 signal nop_pin : std_logic;
59 fetch_st : fetch_stage
68 clk => sys_clk, --: in std_logic;
69 reset => sys_res, --: in std_logic;
72 jump_result => jump_result_pin, --: in instruction_addr_t;
73 prediction_result => prediction_result_pin, --: in instruction_addr_t;
74 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
75 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
78 instruction => instruction_pin, --: out instruction_word_t
79 prog_cnt => prog_cnt_pin
82 decode_st : decode_stage
92 clk => sys_clk, --: in std_logic;
93 reset => sys_res, -- : in std_logic;
96 instruction => instruction_pin, --: in instruction_word_t;
97 prog_cnt => prog_cnt_pin,
98 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
99 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
100 reg_we => reg_we_pin, --: in std_logic;
104 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
105 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
106 to_next_stage => to_next_stage
109 exec_st : execute_stage
111 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
112 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
114 writeback_st : writeback_stage
115 generic map('0', '1')
116 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
117 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
118 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
124 --init : process(all)
127 -- jump_result_pin <= (others => '0');
128 -- alu_jump_bit_pin <= '0';
129 -- reg_w_addr_pin <= (others => '0');
130 -- reg_wr_data_pin <= (others => '0');
131 -- reg_we_pin <= '0';
135 result <= result_pin;
136 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
138 jump_result <= jump_result_pin;
140 reg_wr_data <= reg_wr_data_pin;