cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top is
  10
  11         port(
  12                 --System input pins
  13                    sys_res : in std_logic;
  14                         sys_clk : in std_logic;
  15 --                      result : out gp_register_t;
  16 --                      reg_wr_data : out gp_register_t
  17                   -- uart
  18                         bus_tx : out std_logic;
  19
  20                         sseg0 : out std_logic_vector(0 to 6);
  21                         sseg1 : out std_logic_vector(0 to 6);
  22                         sseg2 : out std_logic_vector(0 to 6);
  23                         sseg3 : out std_logic_vector(0 to 6)
  24                 );
  25
  26 end core_top;
  27
  28 architecture behav of core_top is
  29
  30                 signal jump_result : instruction_addr_t;
  31                 signal jump_result_pin : instruction_addr_t;
  32                 signal prediction_result_pin : instruction_addr_t;
  33                 signal branch_prediction_bit_pin : std_logic;
  34                 signal alu_jump_bit_pin : std_logic;
  35                 signal instruction_pin : instruction_word_t;
  36                 signal prog_cnt_pin : instruction_addr_t;
  37
  38                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  39                 signal reg_wr_data_pin : gp_register_t;
  40                 signal reg_we_pin : std_logic;
  41                 signal to_next_stage : dec_op;
  42
  43 --              signal reg1_rd_data_pin : gp_register_t;
  44 --              signal reg2_rd_data_pin : gp_register_t;
  45
  46                  signal result_pin : gp_register_t;--reg
  47                  signal result_addr_pin : gp_addr_t;--reg
  48                  signal addr_pin : word_t; --memaddr
  49                  signal data_pin : gp_register_t; --mem data --ureg
  50                  signal alu_jump_pin : std_logic;--reg
  51                  signal brpr_pin  : std_logic;  --reg
  52                  signal wr_en_pin : std_logic;--regop --reg
  53                  signal dmem_pin  : std_logic;--memop
  54                  signal dmem_wr_en_pin : std_logic;
  55                  signal hword_pin  : std_logic;
  56                  signal byte_s_pin : std_logic;
  57
  58                  signal gpm_in_pin : extmod_rec;
  59                  signal gpm_out_pin : gp_register_t;
  60                  signal nop_pin : std_logic;
  61
  62                  signal vers, vers_nxt : exec2wb_rec;
  63
  64 begin
  65
  66         fetch_st : fetch_stage
  67                 generic map (
  68
  69                         '0',
  70                         '1'
  71                 )
  72
  73                 port map (
  74                 --System inputs
  75                         clk => sys_clk, --: in std_logic;
  76                         reset => sys_res, --: in std_logic;
  77
  78                 --Data inputs
  79                         jump_result => jump_result_pin, --: in instruction_addr_t;
  80                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  81                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  82                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  83
  84                 --Data outputs
  85                         instruction => instruction_pin, --: out instruction_word_t
  86                         prog_cnt => prog_cnt_pin
  87                 );
  88
  89         decode_st : decode_stage
  90                 generic map (
  91                         -- active reset value
  92                         '0',
  93                         -- active logic value
  94                         '1'
  95
  96                         )
  97                 port map (
  98                 --System inputs
  99                         clk => sys_clk, --: in std_logic;
 100                         reset => sys_res, -- : in std_logic;
 101
 102                 --Data inputs
 103                         instruction => instruction_pin, --: in instruction_word_t;
 104                         prog_cnt => prog_cnt_pin,
 105                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 106                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 107                         reg_we => reg_we_pin, --: in std_logic;
 108                         nop => nop_pin,
 109
 110                 --Data outputs
 111                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 112                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 113                         to_next_stage => to_next_stage
 114                 );
 115
 116           exec_st : execute_stage
 117                 generic map('0')
 118                 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 119                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 120
 121
 122                         vers_nxt.result <= result_pin;
 123                         vers_nxt.result_addr <= result_addr_pin;
 124                         vers_nxt.address <= addr_pin;
 125                         vers_nxt.ram_data <= data_pin;
 126                         vers_nxt.alu_jmp <= alu_jump_pin;
 127                         vers_nxt.br_pred <= brpr_pin;
 128                         vers_nxt.write_en <= wr_en_pin;
 129                         vers_nxt.dmem_en <= dmem_pin;
 130                         vers_nxt.dmem_write_en <= dmem_wr_en_pin;
 131                         vers_nxt.hword <= hword_pin;
 132                         vers_nxt.byte_s <= byte_s_pin;
 133
 134 --          writeback_st : writeback_stage
 135 --                generic map('0', '1')
 136 --                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 137 --                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 138 --                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 139 --
 140
 141                         writeback_st : writeback_stage
 142                 generic map('0', '1')
 143                 port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred,
 144                 vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s,
 145                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 146
 147
 148 syn: process(sys_clk, sys_res)
 149
 150 begin
 151
 152         if sys_res = '0' then
 153                         vers.result <= (others => '0');
 154                         vers.result_addr <= (others => '0');
 155                         vers.address <= (others => '0');
 156                         vers.ram_data <= (others => '0');
 157                         vers.alu_jmp <= '0';
 158                         vers.br_pred <= '0';
 159                         vers.write_en <= '0';
 160                         vers.dmem_en <= '0';
 161                         vers.dmem_write_en <= '0';
 162                         vers.hword <= '0';
 163                         vers.byte_s <= '0';
 164         elsif rising_edge(sys_clk) then
 165                 vers <= vers_nxt;
 166         end if;
 167
 168 end process;
 169
 170
 171 --init : process(all)
 172
 173 --begin
 174 --      jump_result_pin <= (others => '0');
 175 --      alu_jump_bit_pin <= '0';
 176 --      reg_w_addr_pin <= (others => '0');
 177 --      reg_wr_data_pin <= (others => '0');
 178 --      reg_we_pin <= '0';
 179
 180 --end process;
 181
 182 --      result <= result_pin;
 183         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 184
 185         jump_result <= prog_cnt_pin; --jump_result_pin;
 186 --      sys_res <= '1';
 187
 188 --      reg_wr_data <= reg_wr_data_pin;
 189
 190 end behav;