cpu/src/core_pkg.vhd

   1 library IEEE;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.common_pkg.all;
   7
   8 package core_pkg is
   9
  10         component fetch_stage is
  11         generic (
  12                         -- active reset value
  13                         RESET_VALUE : std_logic;
  14                         -- active logic value
  15                         LOGIC_ACT : std_logic;
  16
  17                         );
  18         port(
  19                 --System inputs
  20                         clk : in std_logic;
  21                         reset : in std_logic;
  22
  23                 --Data inputs
  24                         jump_result : in instruction_addr_t;
  25                         prediction_result : in instruction_addr_t;
  26                         branch_prediction_bit : in std_logic;
  27                         alu_jump_bit : in std_logic;
  28
  29                 --Data outputs
  30                         instruction : out instruction_word_t
  31
  32                 );
  33         end component fetch_stage;
  34
  35
  36
  37         component decode_stage is
  38         generic (
  39                         -- active reset value
  40                         RESET_VALUE : std_logic;
  41                         -- active logic value
  42                         LOGIC_ACT : std_logic;
  43
  44                         );
  45         port(
  46                 --System inputs
  47                         clk : in std_logic;
  48                         reset : in std_logic;
  49                 );
  50         end component decode_stage;
  51
  52
  53
  54         component execute_stage is
  55         generic (
  56                         -- active reset value
  57                         RESET_VALUE : std_logic;
  58                         -- active logic value
  59                         LOGIC_ACT : std_logic;
  60
  61                         );
  62         port(
  63                 --System inputs
  64                         clk : in std_logic;
  65                         reset : in std_logic;
  66                 );
  67         end component execute_stage;
  68
  69
  70
  71         component writeback_stage is
  72         generic (
  73                         -- active reset value
  74                         RESET_VALUE : std_logic;
  75                         -- active logic value
  76                         LOGIC_ACT : std_logic;
  77
  78                         );
  79         port(
  80                 --System inputs
  81                         clk : in std_logic;
  82                         reset : in std_logic;
  83                 );
  84         end component writeback_stage;
  85
  86
  87 end package core_pkg;