1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
24 use IEEE.std_logic_1164.all;
25 use IEEE.numeric_std.all;
27 use work.common_pkg.all;
28 use work.extension_pkg.all;
32 component fetch_stage is
35 RESET_VALUE : std_logic;
44 s_reset : in std_logic;
47 jump_result : in instruction_addr_t;
48 prediction_result : in instruction_addr_t;
49 branch_prediction_bit : in std_logic;
50 alu_jump_bit : in std_logic;
51 int_req : in interrupt_t;
52 new_im_data_in : in std_logic;
53 im_addr : in gp_register_t;
54 im_data : in gp_register_t;
57 instruction : out instruction_word_t;
58 prog_cnt : out instruction_addr_t;
62 end component fetch_stage;
66 component decode_stage is
69 RESET_VALUE : std_logic;
80 instruction : in instruction_word_t;
81 prog_cnt : in instruction_addr_t;
82 reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
83 reg_wr_data : in gp_register_t;
84 reg_we : in std_logic;
88 -- reg1_rd_data : out gp_register_t;
89 -- reg2_rd_data : out gp_register_t;
90 branch_prediction_res : out instruction_addr_t;
91 branch_prediction_bit : out std_logic;
93 to_next_stage : out dec_op
95 end component decode_stage;
101 instruction : in instruction_word_t;
102 instr_spl : out instruction_rec
106 end component decoder;
108 component execute_stage is
111 -- active reset value
112 RESET_VALUE : std_logic
113 -- active logic value
114 --LOGIC_ACT : std_logic;
120 reset : in std_logic;
121 dec_instr : in dec_op;
122 regfile_val : in gp_register_t;
123 reg_we : in std_logic;
124 reg_addr : in gp_addr_t;
125 ext_reg : in extmod_rec;
127 result : out gp_register_t;--reg
128 result_addr : out gp_addr_t;--reg
129 addr : out word_t; --memaddr
130 data : out gp_register_t; --mem data --ureg
131 alu_jump : out std_logic;--reg
132 brpr : out std_logic; --reg
133 wr_en : out std_logic;--regop --reg
134 dmem : out std_logic;--memop
135 dmem_write_en : out std_logic;
136 hword : out std_logic;
137 byte_s : out std_logic;
139 ext_data_out : out gp_register_t
141 end component execute_stage;
145 component writeback_stage is
147 -- active reset value
148 RESET_VALUE : std_logic;
149 -- active logic value
150 LOGIC_ACT : std_logic;
157 reset : in std_logic;
159 result : in gp_register_t; --reg (alu result or jumpaddr)
160 result_addr : in gp_addr_t; --reg
161 address : in word_t; --ureg
162 ram_data : in word_t; --ureg
163 alu_jmp : in std_logic; --reg
164 br_pred : in std_logic; --reg
165 write_en : in std_logic; --reg (register file)
166 dmem_en : in std_logic; --ureg (jump addr in mem or in address)
167 dmem_write_en : in std_logic; --ureg
168 hword : in std_logic; --ureg
169 byte_s : in std_logic; --ureg
171 regfile_val : out gp_register_t;
172 reg_we : out std_logic;
173 reg_addr : out gp_addr_t;
174 jump_addr : out instruction_addr_t;
175 jump : out std_logic;
177 bus_tx : out std_logic;
178 bus_rx : in std_logic;
179 new_im_data_out : out std_logic;
180 im_addr : out gp_register_t;
181 im_data : out gp_register_t;
183 --sseg0 : out std_logic_vector(0 to 6);
184 --sseg1 : out std_logic_vector(0 to 6);
185 --sseg2 : out std_logic_vector(0 to 6);
186 --sseg3 : out std_logic_vector(0 to 6);
188 int_req : out interrupt_t
191 end component writeback_stage;
195 end package core_pkg;