3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
10 component fetch_stage is
13 RESET_VALUE : std_logic;
15 LOGIC_ACT : std_logic;
24 jump_result : in instruction_addr_t;
25 prediction_result : in instruction_addr_t;
26 branch_prediction_bit : in std_logic;
27 alu_jump_bit : in std_logic;
30 instruction : out instruction_word_t
33 end component fetch_stage;
37 component decode_stage is
40 RESET_VALUE : std_logic;
42 LOGIC_ACT : std_logic;
51 instruction : in instruction_word_t;
52 reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
53 reg_wr_data : in gp_register_t;
54 reg_we : in std_logic;
57 reg1_rd_data : gp_register_t;
58 reg2_rd_data : gp_register_t;
59 branch_prediction_res : instruction_word_t;
60 branch_prediction_bit : std_logic
62 end component decode_stage;
66 component execute_stage is
69 RESET_VALUE : std_logic;
71 LOGIC_ACT : std_logic;
79 end component execute_stage;
83 component writeback_stage is
86 RESET_VALUE : std_logic;
88 LOGIC_ACT : std_logic;
96 end component writeback_stage;
99 type instruction_rec is record
101 predicates : std_logic_vector(3 downto 0);
105 reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
106 reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
107 reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
109 immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
110 displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
112 jmptype : std_logic_vector(1 downto 0);
114 carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
119 type read_through_write_rec is record
121 rtw_reg : gp_register_t;
122 rtw_reg1 : std_logic;
123 rtw_reg2 : std_logic;
127 end package core_pkg;