cpu/src/core_pkg.vhd

   1 library IEEE;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.common_pkg.all;
   7
   8 package core_pkg is
   9
  10         component fetch_stage is
  11         generic (
  12                         -- active reset value
  13                         RESET_VALUE : std_logic;
  14                         -- active logic value
  15                         LOGIC_ACT : std_logic
  16
  17                         );
  18         port(
  19                 --System inputs
  20                         clk : in std_logic;
  21                         reset : in std_logic;
  22
  23                 --Data inputs
  24                         jump_result : in instruction_addr_t;
  25                         prediction_result : in instruction_addr_t;
  26                         branch_prediction_bit : in std_logic;
  27                         alu_jump_bit : in std_logic;
  28
  29                 --Data outputs
  30                         instruction : out instruction_word_t
  31
  32                 );
  33         end component fetch_stage;
  34
  35
  36
  37         component decode_stage is
  38         generic (
  39                         -- active reset value
  40                         RESET_VALUE : std_logic;
  41                         -- active logic value
  42                         LOGIC_ACT : std_logic
  43
  44                         );
  45         port(
  46                 --System inputs
  47                         clk : in std_logic;
  48                         reset : in std_logic;
  49
  50                 --Data inputs
  51                         instruction : in instruction_word_t;
  52                         reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  53                         reg_wr_data : in gp_register_t;
  54                         reg_we : in std_logic;
  55
  56                 --Data outputs
  57                         reg1_rd_data : out gp_register_t;
  58                         reg2_rd_data : out gp_register_t;
  59                         branch_prediction_res : out instruction_word_t;
  60                         branch_prediction_bit : out std_logic
  61                 );
  62         end component decode_stage;
  63
  64
  65         component decoder is
  66
  67         port(
  68                         instruction : in instruction_word_t;
  69                         instr_spl : out instruction_rec
  70
  71                 );
  72
  73         end component decoder;
  74
  75         component execute_stage is
  76         generic (
  77                         -- active reset value
  78                         RESET_VALUE : std_logic;
  79                         -- active logic value
  80                         LOGIC_ACT : std_logic
  81
  82                         );
  83         port(
  84                 --System inputs
  85                         clk : in std_logic;
  86                         reset : in std_logic
  87                 );
  88         end component execute_stage;
  89
  90
  91
  92         component writeback_stage is
  93         generic (
  94                         -- active reset value
  95                         RESET_VALUE : std_logic;
  96                         -- active logic value
  97                         LOGIC_ACT : std_logic
  98
  99                         );
 100         port(
 101                 --System inputs
 102                         clk : in std_logic;
 103                         reset : in std_logic
 104                 );
 105         end component writeback_stage;
 106
 107
 108
 109 end package core_pkg;