2 use IEEE.std_logic_1164.all;
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3 use IEEE.numeric_std.all;
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5 use work.alu_pkg.all;
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8 architecture behaviour of alu is
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14 reset : in std_logic;
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16 left_operand : in gp_register_t;
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17 right_operand : in gp_register_t;
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18 op_detail : in op_opt_t;
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19 alu_state : in alu_result_rec;
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20 alu_result : out alu_result_rec
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22 end component exec_op;
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24 signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
25 signal left, right : gp_register_t;
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29 add_inst : entity work.exec_op(add_op)
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30 port map(clk,reset,left, right, op_detail, alu_state, add_result);
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32 and_inst : entity work.exec_op(and_op)
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33 port map(clk,reset,left, right, op_detail, alu_state, and_result);
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35 or_inst : entity work.exec_op(or_op)
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36 port map(clk,reset,left, right, op_detail, alu_state, or_result);
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38 xor_inst : entity work.exec_op(xor_op)
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39 port map(clk,reset,left, right, op_detail, alu_state, xor_result);
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41 shift_inst : entity work.exec_op(shift_op)
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42 port map(clk,reset,left, right, op_detail, alu_state, shift_result);
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44 calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
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45 variable result_v : alu_result_rec;
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46 variable res_prod : std_logic;
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47 variable cond_met : std_logic;
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48 variable mem_en : std_logic;
49 variable mem_op : std_logic;
50 variable alu_jmp : std_logic;
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52 result_v := alu_state;
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60 right <= right_operand;
62 addr <= add_result.result;
63 data <= right_operand;
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65 result_v.result := add_result.result;
69 cond_met := not(alu_state.status.zero);
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71 cond_met := alu_state.status.zero;
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73 cond_met := not(alu_state.status.oflo);
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75 cond_met := alu_state.status.oflo;
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77 cond_met := not(alu_state.status.carry);
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79 cond_met := alu_state.status.carry;
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81 cond_met := not(alu_state.status.sign);
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83 cond_met := alu_state.status.sign;
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85 cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);
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87 cond_met := alu_state.status.carry or alu_state.status.zero;
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89 cond_met := not(alu_state.status.sign xor alu_state.status.oflo);
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91 cond_met := alu_state.status.sign xor alu_state.status.oflo;
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93 cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);
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95 cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);
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100 when others => null;
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103 cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
107 result_v := add_result;
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109 result_v := and_result;
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111 result_v := or_result;
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113 result_v := xor_result;
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115 result_v := shift_result;
119 if op_detail(IMM_OPT) = '1' then
120 result_v.result := right_operand;
124 if op_detail(ST_OPT) = '1' then
125 right <= displacement;
129 if op_detail(JMP_REG_OPT) = '0' then
132 result_v.alu_jmp := '1';
133 when JMP_ST_OP => null;
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137 result_v.status.zero := '0';
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138 if result_v.result = REG_ZERO then
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139 result_v.status.zero := '1';
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142 result_v.status.sign := result_v.result(gp_register_t'high);
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144 if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then
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145 result_v.status := alu_state.status;
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148 result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
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149 result_v.mem_en := mem_en and cond_met;
150 result_v.mem_op := mem_op and cond_met;
151 result_v.alu_jmp := alu_jmp and cond_met;
153 alu_result <= result_v;
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157 end architecture behaviour;
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