2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
8 architecture behaviour of alu is
16 left_operand : in gp_register_t;
17 right_operand : in gp_register_t;
18 op_detail : in op_opt_t;
19 alu_state : in alu_result_rec;
20 alu_result : out alu_result_rec
22 end component exec_op;
24 signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
25 signal left_o, right_o : gp_register_t;
29 add_inst : entity work.exec_op(add_op)
30 port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);
32 and_inst : entity work.exec_op(and_op)
33 port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);
35 or_inst : entity work.exec_op(or_op)
36 port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);
38 xor_inst : entity work.exec_op(xor_op)
39 port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);
41 shift_inst : entity work.exec_op(shift_op)
42 port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);
44 calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)
45 variable result_v : alu_result_rec;
46 variable res_prod : std_logic;
47 variable cond_met : std_logic;
48 variable mem_en : std_logic;
49 variable mem_op, hword_op, byte_op : std_logic;
50 variable alu_jump : std_logic;
51 variable nop : std_logic;
53 variable pinc_v, pwr_en_v : std_logic;
55 variable prog_cnt_nxt : std_logic_vector(prog_cnt'range);
57 result_v := alu_state;
66 left_o <= left_operand;
67 right_o <= right_operand;
69 addr <= add_result.result;
70 data <= right_operand;
75 paddr <= (others =>'0');
77 result_v.result := add_result.result;
78 prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
81 cond_met := not(alu_state.status.zero);
83 cond_met := alu_state.status.zero;
85 cond_met := not(alu_state.status.oflo);
87 cond_met := alu_state.status.oflo;
89 cond_met := not(alu_state.status.carry);
91 cond_met := alu_state.status.carry;
93 cond_met := not(alu_state.status.sign);
95 cond_met := alu_state.status.sign;
97 cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);
99 cond_met := alu_state.status.carry or alu_state.status.zero;
101 cond_met := not(alu_state.status.sign xor alu_state.status.oflo);
103 cond_met := alu_state.status.sign xor alu_state.status.oflo;
105 cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);
107 cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);
115 nop := (alu_state.alu_jump xnor alu_state.brpr);
116 cond_met := cond_met and nop;
120 result_v := add_result;
122 result_v := and_result;
124 result_v := or_result;
126 result_v := xor_result;
128 result_v := shift_result;
132 --right_o <= displacement;
133 addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
134 if op_detail(IMM_OPT) = '1' then
135 result_v.result := right_operand;
139 if op_detail(ST_OPT) = '1' then
143 hword_op := op_detail(HWORD_OPT);
144 byte_op := op_detail(BYTE_OPT);
147 if op_detail(JMP_REG_OPT) = '0' then
158 paddr <= (others =>'0');
161 data <= prog_cnt_nxt;
162 if op_detail(RET_OPT) = '1' then
171 if op_detail(PUSH_OPT) = '1' then
178 addr <= std_logic_vector(unsigned(pval_nxt)-4);
184 result_v.status.zero := '0';
185 if result_v.result = REG_ZERO then
186 result_v.status.zero := '1';
189 result_v.status.sign := result_v.result(gp_register_t'high);
191 if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then
192 result_v.status := alu_state.status;
195 result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
196 result_v.mem_en := mem_en and cond_met;
197 result_v.mem_op := mem_op and cond_met;
198 result_v.alu_jump := alu_jump and cond_met;
199 result_v.brpr := brpr and nop;
201 result_v.hw_op := hword_op and cond_met;
202 result_v.byte_op := byte_op and cond_met;
204 pwr_en_v := pwr_en_v and cond_met;
206 if (result_v.alu_jump = '0') and (brpr = '1') then
207 result_v.result := (others => '0');
208 result_v.result(prog_cnt'range) := prog_cnt_nxt;
209 --result_v.reg_op := '1';
212 -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.
213 -- addr <= (others => '0');
215 alu_result <= result_v;
221 end architecture behaviour;