bootromfun: wir kriegen ein 'O' \o/ (wenn man ein 'H' aufn UART schreibt)
[calu.git] / cpu / sim / testcore1.do
1 vlib work
2 vmap work work
3
4 vcom -work work ../src/mem_pkg.vhd
5 vcom -work work ../src/rom.vhd
6 vcom -work work ../src/rom_b.vhd
7 vcom -work work ../src/r_w_ram.vhd
8 vcom -work work ../src/r_w_ram_b.vhd
9 vcom -work work ../src/r2_w_ram.vhd
10 vcom -work work ../src/r2_w_ram_b.vhd
11 vcom -work work ../src/common_pkg.vhd
12 vcom -work work ../src/extension_pkg.vhd
13 vcom -work work ../src/core_pkg.vhd
14 vcom -work work ../src/decoder.vhd
15 vcom -work work ../src/decoder_b.vhd
16 vcom -work work ../src/fetch_stage.vhd
17 vcom -work work ../src/fetch_stage_b.vhd
18 vcom -work work ../src/decode_stage.vhd
19 vcom -work work ../src/decode_stage_b.vhd
20
21 vcom -work work ../src/alu_pkg.vhd
22
23
24 vcom -work work ../src/exec_op.vhd
25 vcom -work work ../src/exec_op/add_op_b.vhd
26 vcom -work work ../src/exec_op/and_op_b.vhd
27 vcom -work work ../src/exec_op/or_op_b.vhd
28 vcom -work work ../src/exec_op/xor_op_b.vhd
29 vcom -work work ../src/exec_op/shift_op_b.vhd
30
31 vcom -work work ../src/alu.vhd
32 vcom -work work ../src/alu_b.vhd
33
34 vcom -work work ../src/gpm.vhd
35 vcom -work work ../src/gpm_b.vhd
36
37 vcom -work work ../src/extension_pkg.vhd
38 vcom -work work ../src/extension.vhd
39 vcom -work work ../src/extension_b.vhd
40
41
42 vcom -work work ../src/extension_imp_pkg.vhd
43 vcom -work work ../src/extension_imp.vhd
44 vcom -work work ../src/extension_imp_b.vhd
45
46 vcom -work work ../src/extension_7seg_pkg.vhd
47 vcom -work work ../src/extension_7seg.vhd
48 vcom -work work ../src/extension_7seg_b.vhd
49
50 vcom -work work ../src/extension_uart_pkg.vhd
51 vcom -work work ../src/rs232_tx.vhd
52 vcom -work work ../src/rs232_tx_arc.vhd
53 vcom -work work ../src/rs232_rx.vhd
54 vcom -work work ../src/rs232_rx_arc.vhd
55 vcom -work work ../src/extension_uart.vhd
56 vcom -work work ../src/extension_uart_b.vhd
57
58 vcom -work work ../src/execute_stage.vhd
59 vcom -work work ../src/execute_stage_b.vhd
60
61
62 vcom -work work ../src/writeback_stage.vhd
63 vcom -work work ../src/writeback_stage_b.vhd
64
65 vcom -work work ../src/pipeline_tb.vhd
66
67 vsim work.pipeline_conf_beh -t ns
68
69 add wave  -group system -format logic /pipeline_tb/sys_clk_pin
70 add wave  -group system -format logic /pipeline_tb/sys_res_n_pin
71
72 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
73 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
74 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
75 add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
76 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
77 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/rom_ram
78 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
79
80 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
81 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl
82 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_dest_addr
83 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src1_addr
84 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src2_addr
85
86 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_we
87 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
88 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
89
90
91
92
93 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
94 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
95 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
96 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg1
97 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg2
98 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
99 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src1
100 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src2
101
102
103
104
105
106
107 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr
108 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.daddr
109 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr1
110 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr2
111 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src1
112 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src2
113 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_we
114 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_addr
115 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/regfile_val
116 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/left_operand
117 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/right_operand
118 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_nxt
119
120
121 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
122 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/reg
123 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result
124 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result_addr
125 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
126 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/br_pred
127 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/write_en
128 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/address
129
130 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_we
131 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
132 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
133
134 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
135 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
136 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
137 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
138 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
139 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
140 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
141
142
143 run 5000 ns