cpu/sim/testcore1.do

   1 vlib work
   2 vmap work work
   3
   4 vcom -work work ../src/mem_pkg.vhd
   5 vcom -work work ../src/r_w_ram.vhd
   6 vcom -work work ../src/r_w_ram_b.vhd
   7 vcom -work work ../src/r2_w_ram.vhd
   8 vcom -work work ../src/r2_w_ram_b.vhd
   9 vcom -work work ../src/common_pkg.vhd
  10 vcom -work work ../src/core_pkg.vhd
  11 vcom -work work ../src/decoder.vhd
  12 vcom -work work ../src/decoder_b.vhd
  13 vcom -work work ../src/fetch_stage.vhd
  14 vcom -work work ../src/fetch_stage_b.vhd
  15 vcom -work work ../src/decode_stage.vhd
  16 vcom -work work ../src/decode_stage_b.vhd
  17
  18 vcom -work work ../src/alu_pkg.vhd
  19 vcom -work work ../src/extension_pkg.vhd
  20
  21
  22 vcom -work work ../src/exec_op.vhd
  23 vcom -work work ../src/exec_op/add_op_b.vhd
  24 vcom -work work ../src/exec_op/and_op_b.vhd
  25 vcom -work work ../src/exec_op/or_op_b.vhd
  26 vcom -work work ../src/exec_op/xor_op_b.vhd
  27 vcom -work work ../src/exec_op/shift_op_b.vhd
  28
  29 vcom -work work ../src/alu.vhd
  30 vcom -work work ../src/alu_b.vhd
  31
  32 vcom -work work ../src/gpm.vhd
  33 vcom -work work ../src/gpm_b.vhd
  34
  35 vcom -work work ../src/extension_pkg.vhd
  36 vcom -work work ../src/extension.vhd
  37 vcom -work work ../src/extension_b.vhd
  38
  39
  40 vcom -work work ../src/extension_uart_pkg.vhd
  41 vcom -work work ../src/rs232_tx.vhd
  42 vcom -work work ../src/rs232_tx_arc.vhd
  43 vcom -work work ../src/extension_uart.vhd
  44 vcom -work work ../src/extension_uart_b.vhd
  45
  46 vcom -work work ../src/execute_stage.vhd
  47 vcom -work work ../src/execute_stage_b.vhd
  48
  49
  50 vcom -work work ../src/writeback_stage.vhd
  51 vcom -work work ../src/writeback_stage_b.vhd
  52
  53 vcom -work work ../src/pipeline_tb.vhd
  54
  55 vsim work.pipeline_conf_beh -t ns
  56
  57 add wave  -group system -format logic /pipeline_tb/sys_clk_pin
  58 add wave  -group system -format logic /pipeline_tb/sys_res_n_pin
  59
  60 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
  61 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
  62 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
  63 add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
  64 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
  65 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
  66
  67 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
  68 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl
  69 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_dest_addr
  70 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src1_addr
  71 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src2_addr
  72
  73 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_we
  74 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
  75 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
  76
  77
  78
  79
  80 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
  81 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
  82 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
  83 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg1
  84 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg2
  85 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
  86 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src1
  87 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src2
  88
  89
  90
  91
  92
  93
  94 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr
  95 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.daddr
  96 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr1
  97 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr2
  98 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src1
  99 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src2
 100 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_we
 101 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_addr
 102 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/regfile_val
 103 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/left_operand
 104 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/right_operand
 105 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_nxt
 106
 107
 108 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
 109 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/reg
 110 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result
 111 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result_addr
 112 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
 113 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/br_pred
 114 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/write_en
 115 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/address
 116
 117 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_we
 118 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 119 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 120
 121
 122
 123 run 5000 ns