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3 # and other software and tools, and its AMPP partner logic
4 # functions, and any output files from any of the foregoing
5 # (including device programming or simulation files), and any
6 # associated documentation or information are expressly subject
7 # to the terms and conditions of the Altera Program License
8 # Subscription Agreement, Altera MegaCore Function License
9 # Agreement, or other applicable license agreement, including,
10 # without limitation, that your use is for the sole purpose of
11 # programming logic devices manufactured by Altera and sold by
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13 # applicable agreement for further details.
15 # Quartus II: Generate Tcl File for Project
17 # Generated on: Thu Dec 23 21:48:06 2010
19 # Load Quartus II Tcl Project package
20 package require ::quartus::project
22 set need_to_close_project 0
23 set make_assignments 1
25 # Check that the right project is open
26 if {[is_project_open]} {
27 if {[string compare $quartus(project) "dt"]} {
28 puts "Project dt is not open"
29 set make_assignments 0
32 # Only open if not already open
33 if {[project_exists dt]} {
34 project_open -revision dt dt
36 project_new -revision dt dt
38 set need_to_close_project 1
42 if {$make_assignments} {
43 set_global_assignment -name FAMILY Cyclone
44 set_global_assignment -name DEVICE EP1C12Q240C8
45 set_global_assignment -name TOP_LEVEL_ENTITY core_top
46 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
47 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
48 set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
49 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
50 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
51 set_global_assignment -name GENERATE_RBF_FILE ON
52 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
53 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
54 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
55 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
56 set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
57 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
58 set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
59 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
60 set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
61 set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
62 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
63 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
64 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
65 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
66 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
67 set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
68 set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
69 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
70 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
71 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
72 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
73 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
74 set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
75 set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
76 set_global_assignment -name VHDL_FILE ../src/rom.vhd
77 set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
78 set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
79 set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
80 set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
81 set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
82 set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
83 set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
84 set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
85 set_global_assignment -name VHDL_FILE ../src/rw_r_ram_b.vhd
86 set_global_assignment -name VHDL_FILE ../src/rw_r_ram.vhd
87 set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
88 set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
89 set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
90 set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
91 set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
92 set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
93 set_global_assignment -name VHDL_FILE ../src/pipeline_tb.vhd
94 set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
95 set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
96 set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
97 set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
98 set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
99 set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
100 set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
101 set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
102 set_global_assignment -name VHDL_FILE ../src/extension.vhd
103 set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
104 set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
105 set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
106 set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
107 set_global_assignment -name VHDL_FILE ../src/decoder.vhd
108 set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
109 set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
110 set_global_assignment -name VHDL_FILE ../src/core_top.vhd
111 set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
112 set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
113 set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
114 set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
115 set_global_assignment -name VHDL_FILE ../src/alu.vhd
116 set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
117 set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
118 set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
119 set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
120 set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
121 set_global_assignment -name SMART_RECOMPILE ON
122 set_global_assignment -name ENABLE_CLOCK_LATENCY ON
123 set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
124 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
125 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
126 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
127 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
128 set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
129 set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
130 set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
131 set_location_assignment PIN_152 -to sys_clk
132 set_location_assignment PIN_42 -to sys_res
133 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
139 if {$need_to_close_project} {