cpu/create_project.tcl

   1 package require ::quartus::project
   2
   3 set need_to_close_project 0
   4 set make_assignments 1
   5
   6 # Check that the right project is open
   7 if {[is_project_open]} {
   8         if {[string compare $quartus(project) "de1_cyclone"]} {
   9                 puts "Project de1_cyclone is not open"
  10                 set make_assignments 0
  11         }
  12 } else {
  13         # Only open if not already open
  14         if {[project_exists de1_cyclone]} {
  15                 project_open -revision de1_cyclone de1_cyclone
  16         } else {
  17                 project_new -revision de1_cyclone de1_cyclone
  18         }
  19         set need_to_close_project 1
  20 }
  21
  22 # Make assignments
  23 if {$make_assignments} {
  24         set_global_assignment -name FAMILY "Cyclone II"
  25         set_global_assignment -name DEVICE EP2C20F484C7
  26         set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
  27         set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
  28         set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
  29         set_global_assignment -name MISC_FILE "de1_cyclone.dpf"
  30         set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
  31         set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
  32         set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
  33
  34         set_global_assignment -name TOP_LEVEL_ENTITY core_top
  35         set_global_assignment -name VHDL_FILE ../src/core_top.vhd
  36         set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
  37         set_global_assignment -name VHDL_FILE ../src/rom.vhd
  38         set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
  39         set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
  40         set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
  41         set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
  42         set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
  43         set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
  44         set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
  45         set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
  46         set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
  47         set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
  48         set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
  49         set_global_assignment -name VHDL_FILE ../src/decoder.vhd
  50         set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
  51         set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
  52         set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
  53
  54         set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
  55         set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
  56         set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
  57         set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
  58         set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
  59         set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
  60         set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
  61         set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
  62         set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
  63         set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
  64         set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
  65
  66         set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
  67
  68         set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
  69 #       set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
  70         set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
  71         set_global_assignment -name VHDL_FILE ../src/extension.vhd
  72         set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
  73
  74         set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
  75         set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
  76         set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
  77         set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
  78         set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
  79         set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
  80
  81         set_global_assignment -name VHDL_FILE ../src/alu.vhd
  82         set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
  83
  84 #       set_global_assignment -name VHDL_FILE ../src/gpm.vhd
  85 #       set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd
  86
  87         set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
  88         set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
  89
  90
  91         set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
  92         set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
  93
  94
  95         set_location_assignment PIN_L1 -to sys_clk
  96         set_location_assignment PIN_R22 -to sys_res
  97         set_location_assignment PIN_G12 -to bus_tx
  98         set_location_assignment PIN_F14 -to bus_rx
  99
 100         set_location_assignment PIN_J2 -to sseg0[0]
 101         set_location_assignment PIN_J1 -to sseg0[1]
 102         set_location_assignment PIN_H2 -to sseg0[2]
 103         set_location_assignment PIN_H1 -to sseg0[3]
 104         set_location_assignment PIN_F2 -to sseg0[4]
 105         set_location_assignment PIN_F1 -to sseg0[5]
 106         set_location_assignment PIN_E2 -to sseg0[6]
 107
 108         set_location_assignment PIN_E1 -to sseg1[0]
 109         set_location_assignment PIN_H6 -to sseg1[1]
 110         set_location_assignment PIN_H5 -to sseg1[2]
 111         set_location_assignment PIN_H4 -to sseg1[3]
 112         set_location_assignment PIN_G3 -to sseg1[4]
 113         set_location_assignment PIN_D2 -to sseg1[5]
 114         set_location_assignment PIN_D1 -to sseg1[6]
 115
 116         set_location_assignment PIN_G5 -to sseg2[0]
 117         set_location_assignment PIN_G6 -to sseg2[1]
 118         set_location_assignment PIN_C2 -to sseg2[2]
 119         set_location_assignment PIN_C1 -to sseg2[3]
 120         set_location_assignment PIN_E3 -to sseg2[4]
 121         set_location_assignment PIN_E4 -to sseg2[5]
 122         set_location_assignment PIN_D3 -to sseg2[6]
 123
 124         set_location_assignment PIN_F4 -to sseg3[0]
 125         set_location_assignment PIN_D5 -to sseg3[1]
 126         set_location_assignment PIN_D6 -to sseg3[2]
 127         set_location_assignment PIN_J4 -to sseg3[3]
 128         set_location_assignment PIN_L8 -to sseg3[4]
 129         set_location_assignment PIN_F3 -to sseg3[5]
 130         set_location_assignment PIN_D4 -to sseg3[6]
 131
 132
 133         set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
 134         set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
 135
 136         set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
 137         set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 138         set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 139         set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 140         set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 141
 142         # Commit assignments
 143         export_assignments
 144
 145         # Close project
 146         if {$need_to_close_project} {
 147                 project_close
 148         }
 149 }