5 \begin{tabular}{|c|c|c|c|}\hline
6 Bitcode & Condition & Bits to test & suffixes \\ \hline
7 0000 & not equal / not zero & ZF = 0 & nq, nz \\ \hline
8 0001 & equal / zero & ZF = 1 & eq, zs \\ \hline
9 0010 & not overflow & OF = 0 & no \\ \hline
10 0011 & overflow & OF = 1 & ov \\ \hline
11 0100 & not carry / above e q & CF = 0 & nc, ae \\ \hline
12 0101 & carry / below & CF = 1 & cs, bl \\ \hline
13 0110 & not signed / not neg. & SF = 0 & ns, nn \\ \hline
14 0111 & signed / neg. & SF = 1 & ss, ns \\ \hline
15 1000 & above & (CF == 0 $\wedge$ ZF == 0) & ab \\ \hline
16 1001 & below or equal & (CF == 1 $\vee$ ZF == 1) & be \\ \hline
17 1010 & greater than or equal & SF == OF & ge \\ \hline
18 1011 & less than & SF != OF & lt \\ \hline
19 1100 & greater than & (ZF == 0 $\wedge$ SF == OF) & gt \\ \hline
20 1101 & less than or equal & (ZF == 1 $\vee$ SF != OF) & le \\ \hline
21 1110 & always & & \texttt{none} \\ \hline
22 1111 & never & & nv \\ \hline
24 \caption{codierung von conditions WARNING! may contain BUGS!!}
28 above and below are for unsigned, greater and less for signed values
30 note: it seams that the definition of conditions on unsigned values depend on the instruction set. below is CF = 1 by x86/amd64 and avr, CF = 0 by arm. when cmp is defined as cmp r1, r2 == r1-r2 == is r1 COND r2 then arm looks more saner. the conditons marked with a X in the bitcode are open for change because of this unclear situation \Large{RFC} \normalsize
34 \begin{tabular}{|l|c|c|c|c|} \hline
35 Bit & 3 & 2 & 1 & 0 \\ \hline
36 Flag & SF & CF & OF & ZF \\ \hline
38 \caption{billig PSW bitorder}