1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/exceptions.h"
44 #include "vm/jit/abi.h"
45 #include "vm/jit/abi-asm.h"
46 #include "vm/jit/asmpart.h"
47 #include "vm/jit/codegen-common.h"
48 #include "vm/jit/emit-common.h"
49 #include "vm/jit/jit.h"
50 #include "vm/jit/patcher-common.h"
51 #include "vm/jit/replace.h"
52 #include "vm/jit/trace.h"
54 #include "vmcore/options.h"
57 /* emit_load *******************************************************************
59 Emits a possible load of an operand.
61 *******************************************************************************/
63 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
69 /* get required compiler data */
73 if (IS_INMEMORY(src->flags)) {
76 disp = src->vv.regoff;
80 M_ILD(tempreg, REG_SP, disp);
84 M_LLD(tempreg, REG_SP, disp);
87 M_FLD(tempreg, REG_SP, disp);
90 M_DLD(tempreg, REG_SP, disp);
93 vm_abort("emit_load: unknown type %d", src->type);
105 /* emit_store ******************************************************************
107 This function generates the code to store the result of an
108 operation back into a spilled pseudo-variable. If the
109 pseudo-variable has not been spilled in the first place, this
110 function will generate nothing.
112 *******************************************************************************/
114 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
123 /* get required compiler data */
128 /* do we have to generate a conditional move? */
130 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
131 /* the passed register d is actually the source register */
135 /* Only pass the opcode to codegen_reg_of_var to get the real
136 destination register. */
138 opcode = iptr->opc & ICMD_OPCODE_MASK;
140 /* get the real destination register */
142 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
144 /* and emit the conditional move */
146 emit_cmovxx(cd, iptr, s, d);
150 if (IS_INMEMORY(dst->flags)) {
153 disp = dst->vv.regoff;
159 M_LST(d, REG_SP, disp);
162 M_FST(d, REG_SP, disp);
165 M_DST(d, REG_SP, disp);
168 vm_abort("emit_store: unknown type %d", dst->type);
174 /* emit_copy *******************************************************************
176 Generates a register/memory to register/memory copy.
178 *******************************************************************************/
180 void emit_copy(jitdata *jd, instruction *iptr)
187 /* get required compiler data */
191 /* get source and destination variables */
193 src = VAROP(iptr->s1);
194 dst = VAROP(iptr->dst);
196 if ((src->vv.regoff != dst->vv.regoff) ||
197 ((src->flags ^ dst->flags) & INMEMORY)) {
199 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
200 /* emit nothing, as the value won't be used anyway */
204 /* If one of the variables resides in memory, we can eliminate
205 the register move from/to the temporary register with the
206 order of getting the destination register and the load. */
208 if (IS_INMEMORY(src->flags)) {
209 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
210 s1 = emit_load(jd, iptr, src, d);
213 s1 = emit_load(jd, iptr, src, REG_IFTMP);
214 d = codegen_reg_of_var(iptr->opc, dst, s1);
229 vm_abort("emit_copy: unknown type %d", src->type);
233 emit_store(jd, iptr, dst, d);
238 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
241 switch (iptr->flags.fields.condition) {
265 /* emit_branch *****************************************************************
267 Emits the code for conditional and unconditional branchs.
269 *******************************************************************************/
271 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
275 /* NOTE: A displacement overflow cannot happen. */
277 /* check which branch to generate */
279 if (condition == BRANCH_UNCONDITIONAL) {
281 /* calculate the different displacements */
283 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
285 M_JMP_IMM(branchdisp);
288 /* calculate the different displacements */
290 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
324 vm_abort("emit_branch: unknown condition %d", condition);
330 /* emit_arithmetic_check *******************************************************
332 Emit an ArithmeticException check.
334 *******************************************************************************/
336 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
338 if (INSTRUCTION_MUST_CHECK(iptr)) {
341 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
346 /* emit_arrayindexoutofbounds_check ********************************************
348 Emit a ArrayIndexOutOfBoundsException check.
350 *******************************************************************************/
352 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
354 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
356 M_ICMP(REG_ITMP3, s2);
358 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
363 /* emit_arraystore_check *******************************************************
365 Emit an ArrayStoreException check.
367 *******************************************************************************/
369 void emit_arraystore_check(codegendata *cd, instruction *iptr)
371 if (INSTRUCTION_MUST_CHECK(iptr)) {
374 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_ARRAYSTORE);
379 /* emit_classcast_check ********************************************************
381 Emit a ClassCastException check.
383 *******************************************************************************/
385 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
387 if (INSTRUCTION_MUST_CHECK(iptr)) {
399 vm_abort("emit_classcast_check: unknown condition %d", condition);
401 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
406 /* emit_nullpointer_check ******************************************************
408 Emit a NullPointerException check.
410 *******************************************************************************/
412 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
414 if (INSTRUCTION_MUST_CHECK(iptr)) {
417 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
422 /* emit_exception_check ********************************************************
424 Emit an Exception check.
426 *******************************************************************************/
428 void emit_exception_check(codegendata *cd, instruction *iptr)
430 if (INSTRUCTION_MUST_CHECK(iptr)) {
433 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
438 /* emit_trap_compiler **********************************************************
440 Emit a trap instruction which calls the JIT compiler.
442 *******************************************************************************/
444 void emit_trap_compiler(codegendata *cd)
446 M_ALD_MEM(REG_METHODPTR, EXCEPTION_HARDWARE_COMPILER);
450 /* emit_trap *******************************************************************
452 Emit a trap instruction and return the original machine code.
454 *******************************************************************************/
456 uint32_t emit_trap(codegendata *cd)
460 /* Get machine code which is patched back in later. The trap is 2
463 mcode = *((uint16_t *) cd->mcodeptr);
465 /* XXX This needs to be change to INT3 when the debugging problems
466 with gdb are resolved. */
474 /* emit_verbosecall_enter ******************************************************
476 Generates the code for the call trace.
478 *******************************************************************************/
481 void emit_verbosecall_enter(jitdata *jd)
490 /* get required compiler data */
498 /* mark trace code */
502 /* keep 16-byte stack alignment */
504 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
505 ALIGN_2(stackframesize);
507 M_LSUB_IMM(stackframesize * 8, REG_SP);
509 /* save argument registers */
511 for (i = 0; i < md->paramcount; i++) {
512 if (!md->params[i].inmemory) {
513 s = md->params[i].regoff;
515 switch (md->paramtypes[i].type) {
519 M_LST(s, REG_SP, i * 8);
523 M_DST(s, REG_SP, i * 8);
529 /* save all argument and temporary registers for leaf methods */
531 if (jd->isleafmethod) {
532 for (i = 0; i < INT_ARG_CNT; i++)
533 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
535 for (i = 0; i < FLT_ARG_CNT; i++)
536 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
538 for (i = 0; i < INT_TMP_CNT; i++)
539 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
541 for (i = 0; i < FLT_TMP_CNT; i++)
542 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
545 M_MOV_IMM(m, REG_A0);
546 M_MOV(REG_SP, REG_A1);
547 M_MOV(REG_SP, REG_A2);
548 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
549 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
552 /* restore argument registers */
554 for (i = 0; i < md->paramcount; i++) {
555 if (!md->params[i].inmemory) {
556 s = md->params[i].regoff;
558 switch (md->paramtypes[i].type) {
562 M_LLD(s, REG_SP, i * 8);
566 M_DLD(s, REG_SP, i * 8);
573 /* restore all argument and temporary registers for leaf methods */
575 if (jd->isleafmethod) {
576 for (i = 0; i < INT_ARG_CNT; i++)
577 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
579 for (i = 0; i < FLT_ARG_CNT; i++)
580 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
582 for (i = 0; i < INT_TMP_CNT; i++)
583 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
585 for (i = 0; i < FLT_TMP_CNT; i++)
586 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
589 M_LADD_IMM(stackframesize * 8, REG_SP);
591 /* mark trace code */
595 #endif /* !defined(NDEBUG) */
598 /* emit_verbosecall_exit *******************************************************
600 Generates the code for the call trace.
602 *******************************************************************************/
605 void emit_verbosecall_exit(jitdata *jd)
612 /* get required compiler data */
620 /* mark trace code */
624 /* keep 16-byte stack alignment */
626 M_ASUB_IMM(2 * 8, REG_SP);
628 /* save return value */
630 switch (md->returntype.type) {
634 M_LST(REG_RESULT, REG_SP, 0 * 8);
638 M_DST(REG_FRESULT, REG_SP, 0 * 8);
642 M_MOV_IMM(m, REG_A0);
643 M_MOV(REG_SP, REG_A1);
645 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
648 /* restore return value */
650 switch (md->returntype.type) {
654 M_LLD(REG_RESULT, REG_SP, 0 * 8);
658 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
662 M_AADD_IMM(2 * 8, REG_SP);
664 /* mark trace code */
668 #endif /* !defined(NDEBUG) */
671 /* code generation functions **************************************************/
673 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
675 if ((basereg == REG_SP) || (basereg == R12)) {
677 emit_address_byte(0, dreg, REG_SP);
678 emit_address_byte(0, REG_SP, REG_SP);
680 } else if (IS_IMM8(disp)) {
681 emit_address_byte(1, dreg, REG_SP);
682 emit_address_byte(0, REG_SP, REG_SP);
686 emit_address_byte(2, dreg, REG_SP);
687 emit_address_byte(0, REG_SP, REG_SP);
691 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
692 emit_address_byte(0,(dreg),(basereg));
694 } else if ((basereg) == RIP) {
695 emit_address_byte(0, dreg, RBP);
700 emit_address_byte(1, dreg, basereg);
704 emit_address_byte(2, dreg, basereg);
711 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
713 if ((basereg == REG_SP) || (basereg == R12)) {
714 emit_address_byte(2, dreg, REG_SP);
715 emit_address_byte(0, REG_SP, REG_SP);
719 emit_address_byte(2, dreg, basereg);
725 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
728 emit_address_byte(0, reg, 4);
729 emit_address_byte(scale, indexreg, 5);
732 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
733 emit_address_byte(0, reg, 4);
734 emit_address_byte(scale, indexreg, basereg);
736 else if (IS_IMM8(disp)) {
737 emit_address_byte(1, reg, 4);
738 emit_address_byte(scale, indexreg, basereg);
742 emit_address_byte(2, reg, 4);
743 emit_address_byte(scale, indexreg, basereg);
749 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
752 varinfo *v_s1,*v_s2,*v_dst;
755 /* get required compiler data */
759 v_s1 = VAROP(iptr->s1);
760 v_s2 = VAROP(iptr->sx.s23.s2);
761 v_dst = VAROP(iptr->dst);
763 s1 = v_s1->vv.regoff;
764 s2 = v_s2->vv.regoff;
765 d = v_dst->vv.regoff;
767 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
769 if (IS_INMEMORY(v_dst->flags)) {
770 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
772 M_ILD(RCX, REG_SP, s2);
773 emit_shiftl_membase(cd, shift_op, REG_SP, d);
776 M_ILD(RCX, REG_SP, s2);
777 M_ILD(REG_ITMP2, REG_SP, s1);
778 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
779 M_IST(REG_ITMP2, REG_SP, d);
782 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
783 /* s1 may be equal to RCX */
786 M_ILD(REG_ITMP1, REG_SP, s2);
787 M_IST(s1, REG_SP, d);
788 M_INTMOVE(REG_ITMP1, RCX);
791 M_IST(s1, REG_SP, d);
792 M_ILD(RCX, REG_SP, s2);
796 M_ILD(RCX, REG_SP, s2);
797 M_IST(s1, REG_SP, d);
800 emit_shiftl_membase(cd, shift_op, REG_SP, d);
802 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
805 emit_shiftl_membase(cd, shift_op, REG_SP, d);
809 M_ILD(REG_ITMP2, REG_SP, s1);
810 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
811 M_IST(REG_ITMP2, REG_SP, d);
815 /* s1 may be equal to RCX */
816 M_IST(s1, REG_SP, d);
818 emit_shiftl_membase(cd, shift_op, REG_SP, d);
821 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
829 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
830 M_ILD(RCX, REG_SP, s2);
831 M_ILD(d, REG_SP, s1);
832 emit_shiftl_reg(cd, shift_op, d);
834 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
835 /* s1 may be equal to RCX */
837 M_ILD(RCX, REG_SP, s2);
838 emit_shiftl_reg(cd, shift_op, d);
840 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
842 M_ILD(d, REG_SP, s1);
843 emit_shiftl_reg(cd, shift_op, d);
846 /* s1 may be equal to RCX */
849 /* d cannot be used to backup s1 since this would
851 M_INTMOVE(s1, REG_ITMP3);
853 M_INTMOVE(REG_ITMP3, d);
861 /* d may be equal to s2 */
865 emit_shiftl_reg(cd, shift_op, d);
869 M_INTMOVE(REG_ITMP3, RCX);
871 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
876 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
879 varinfo *v_s1,*v_s2,*v_dst;
882 /* get required compiler data */
886 v_s1 = VAROP(iptr->s1);
887 v_s2 = VAROP(iptr->sx.s23.s2);
888 v_dst = VAROP(iptr->dst);
890 s1 = v_s1->vv.regoff;
891 s2 = v_s2->vv.regoff;
892 d = v_dst->vv.regoff;
894 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
896 if (IS_INMEMORY(v_dst->flags)) {
897 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
899 M_ILD(RCX, REG_SP, s2);
900 emit_shift_membase(cd, shift_op, REG_SP, d);
903 M_ILD(RCX, REG_SP, s2);
904 M_LLD(REG_ITMP2, REG_SP, s1);
905 emit_shift_reg(cd, shift_op, REG_ITMP2);
906 M_LST(REG_ITMP2, REG_SP, d);
909 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
910 /* s1 may be equal to RCX */
913 M_ILD(REG_ITMP1, REG_SP, s2);
914 M_LST(s1, REG_SP, d);
915 M_INTMOVE(REG_ITMP1, RCX);
918 M_LST(s1, REG_SP, d);
919 M_ILD(RCX, REG_SP, s2);
923 M_ILD(RCX, REG_SP, s2);
924 M_LST(s1, REG_SP, d);
927 emit_shift_membase(cd, shift_op, REG_SP, d);
929 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
932 emit_shift_membase(cd, shift_op, REG_SP, d);
936 M_LLD(REG_ITMP2, REG_SP, s1);
937 emit_shift_reg(cd, shift_op, REG_ITMP2);
938 M_LST(REG_ITMP2, REG_SP, d);
942 /* s1 may be equal to RCX */
943 M_LST(s1, REG_SP, d);
945 emit_shift_membase(cd, shift_op, REG_SP, d);
948 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
956 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
957 M_ILD(RCX, REG_SP, s2);
958 M_LLD(d, REG_SP, s1);
959 emit_shift_reg(cd, shift_op, d);
961 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
962 /* s1 may be equal to RCX */
964 M_ILD(RCX, REG_SP, s2);
965 emit_shift_reg(cd, shift_op, d);
967 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
969 M_LLD(d, REG_SP, s1);
970 emit_shift_reg(cd, shift_op, d);
973 /* s1 may be equal to RCX */
976 /* d cannot be used to backup s1 since this would
978 M_INTMOVE(s1, REG_ITMP3);
980 M_INTMOVE(REG_ITMP3, d);
988 /* d may be equal to s2 */
992 emit_shift_reg(cd, shift_op, d);
996 M_INTMOVE(REG_ITMP3, RCX);
998 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1003 /* low-level code emitter functions *******************************************/
1005 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1007 emit_rex(1,(reg),0,(dreg));
1008 *(cd->mcodeptr++) = 0x89;
1009 emit_reg((reg),(dreg));
1013 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1015 emit_rex(1,0,0,(reg));
1016 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1021 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1023 emit_rex(0,(reg),0,(dreg));
1024 *(cd->mcodeptr++) = 0x89;
1025 emit_reg((reg),(dreg));
1029 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1030 emit_rex(0,0,0,(reg));
1031 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1036 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1037 emit_rex(1,(reg),0,(basereg));
1038 *(cd->mcodeptr++) = 0x8b;
1039 emit_membase(cd, (basereg),(disp),(reg));
1044 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1045 * constant membase immediate length of 32bit
1047 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1048 emit_rex(1,(reg),0,(basereg));
1049 *(cd->mcodeptr++) = 0x8b;
1050 emit_membase32(cd, (basereg),(disp),(reg));
1054 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1056 emit_rex(0,(reg),0,(basereg));
1057 *(cd->mcodeptr++) = 0x8b;
1058 emit_membase(cd, (basereg),(disp),(reg));
1062 /* ATTENTION: Always emit a REX byte, because the instruction size can
1063 be smaller when all register indexes are smaller than 7. */
1064 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1066 emit_byte_rex((reg),0,(basereg));
1067 *(cd->mcodeptr++) = 0x8b;
1068 emit_membase32(cd, (basereg),(disp),(reg));
1072 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1073 emit_rex(1,(reg),0,(basereg));
1074 *(cd->mcodeptr++) = 0x89;
1075 emit_membase(cd, (basereg),(disp),(reg));
1079 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1080 emit_rex(1,(reg),0,(basereg));
1081 *(cd->mcodeptr++) = 0x89;
1082 emit_membase32(cd, (basereg),(disp),(reg));
1086 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1087 emit_rex(0,(reg),0,(basereg));
1088 *(cd->mcodeptr++) = 0x89;
1089 emit_membase(cd, (basereg),(disp),(reg));
1093 /* Always emit a REX byte, because the instruction size can be smaller when */
1094 /* all register indexes are smaller than 7. */
1095 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1096 emit_byte_rex((reg),0,(basereg));
1097 *(cd->mcodeptr++) = 0x89;
1098 emit_membase32(cd, (basereg),(disp),(reg));
1102 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1103 emit_rex(1,(reg),(indexreg),(basereg));
1104 *(cd->mcodeptr++) = 0x8b;
1105 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1109 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1110 emit_rex(0,(reg),(indexreg),(basereg));
1111 *(cd->mcodeptr++) = 0x8b;
1112 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1116 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1117 emit_rex(1,(reg),(indexreg),(basereg));
1118 *(cd->mcodeptr++) = 0x89;
1119 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1123 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1124 emit_rex(0,(reg),(indexreg),(basereg));
1125 *(cd->mcodeptr++) = 0x89;
1126 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1130 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1131 *(cd->mcodeptr++) = 0x66;
1132 emit_rex(0,(reg),(indexreg),(basereg));
1133 *(cd->mcodeptr++) = 0x89;
1134 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1138 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1139 emit_byte_rex((reg),(indexreg),(basereg));
1140 *(cd->mcodeptr++) = 0x88;
1141 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1145 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1146 emit_rex(1,0,0,(basereg));
1147 *(cd->mcodeptr++) = 0xc7;
1148 emit_membase(cd, (basereg),(disp),0);
1153 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1154 emit_rex(1,0,0,(basereg));
1155 *(cd->mcodeptr++) = 0xc7;
1156 emit_membase32(cd, (basereg),(disp),0);
1161 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1162 emit_rex(0,0,0,(basereg));
1163 *(cd->mcodeptr++) = 0xc7;
1164 emit_membase(cd, (basereg),(disp),0);
1169 /* Always emit a REX byte, because the instruction size can be smaller when */
1170 /* all register indexes are smaller than 7. */
1171 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1172 emit_byte_rex(0,0,(basereg));
1173 *(cd->mcodeptr++) = 0xc7;
1174 emit_membase32(cd, (basereg),(disp),0);
1179 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1181 emit_rex(1,(dreg),0,(reg));
1182 *(cd->mcodeptr++) = 0x0f;
1183 *(cd->mcodeptr++) = 0xbe;
1184 /* XXX: why do reg and dreg have to be exchanged */
1185 emit_reg((dreg),(reg));
1189 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1191 emit_rex(1,(dreg),0,(reg));
1192 *(cd->mcodeptr++) = 0x0f;
1193 *(cd->mcodeptr++) = 0xbf;
1194 /* XXX: why do reg and dreg have to be exchanged */
1195 emit_reg((dreg),(reg));
1199 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1201 emit_rex(1,(dreg),0,(reg));
1202 *(cd->mcodeptr++) = 0x63;
1203 /* XXX: why do reg and dreg have to be exchanged */
1204 emit_reg((dreg),(reg));
1208 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1210 emit_rex(1,(dreg),0,(reg));
1211 *(cd->mcodeptr++) = 0x0f;
1212 *(cd->mcodeptr++) = 0xb7;
1213 /* XXX: why do reg and dreg have to be exchanged */
1214 emit_reg((dreg),(reg));
1218 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1219 emit_rex(1,(reg),(indexreg),(basereg));
1220 *(cd->mcodeptr++) = 0x0f;
1221 *(cd->mcodeptr++) = 0xbf;
1222 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1226 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1227 emit_rex(1,(reg),(indexreg),(basereg));
1228 *(cd->mcodeptr++) = 0x0f;
1229 *(cd->mcodeptr++) = 0xbe;
1230 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1234 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1235 emit_rex(1,(reg),(indexreg),(basereg));
1236 *(cd->mcodeptr++) = 0x0f;
1237 *(cd->mcodeptr++) = 0xb7;
1238 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1242 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1244 emit_rex(1,0,(indexreg),(basereg));
1245 *(cd->mcodeptr++) = 0xc7;
1246 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1251 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1253 emit_rex(0,0,(indexreg),(basereg));
1254 *(cd->mcodeptr++) = 0xc7;
1255 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1260 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1262 *(cd->mcodeptr++) = 0x66;
1263 emit_rex(0,0,(indexreg),(basereg));
1264 *(cd->mcodeptr++) = 0xc7;
1265 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1270 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1272 emit_rex(0,0,(indexreg),(basereg));
1273 *(cd->mcodeptr++) = 0xc6;
1274 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1279 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1281 emit_rex(1, dreg, 0, 0);
1282 *(cd->mcodeptr++) = 0x8b;
1283 emit_address_byte(0, dreg, 4);
1291 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1293 emit_rex(1,(reg),0,(dreg));
1294 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1295 emit_reg((reg),(dreg));
1299 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1301 emit_rex(0,(reg),0,(dreg));
1302 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1303 emit_reg((reg),(dreg));
1307 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1309 emit_rex(1,(reg),0,(basereg));
1310 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1311 emit_membase(cd, (basereg),(disp),(reg));
1315 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1317 emit_rex(0,(reg),0,(basereg));
1318 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1319 emit_membase(cd, (basereg),(disp),(reg));
1323 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1325 emit_rex(1,(reg),0,(basereg));
1326 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1327 emit_membase(cd, (basereg),(disp),(reg));
1331 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1333 emit_rex(0,(reg),0,(basereg));
1334 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1335 emit_membase(cd, (basereg),(disp),(reg));
1339 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1341 emit_rex(1,0,0,(dreg));
1342 *(cd->mcodeptr++) = 0x83;
1343 emit_reg((opc),(dreg));
1346 emit_rex(1,0,0,(dreg));
1347 *(cd->mcodeptr++) = 0x81;
1348 emit_reg((opc),(dreg));
1354 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1356 emit_rex(1,0,0,(dreg));
1357 *(cd->mcodeptr++) = 0x81;
1358 emit_reg((opc),(dreg));
1363 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1365 emit_rex(0,0,0,(dreg));
1366 *(cd->mcodeptr++) = 0x81;
1367 emit_reg((opc),(dreg));
1372 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1374 emit_rex(0,0,0,(dreg));
1375 *(cd->mcodeptr++) = 0x83;
1376 emit_reg((opc),(dreg));
1379 emit_rex(0,0,0,(dreg));
1380 *(cd->mcodeptr++) = 0x81;
1381 emit_reg((opc),(dreg));
1387 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1389 emit_rex(1,(basereg),0,0);
1390 *(cd->mcodeptr++) = 0x83;
1391 emit_membase(cd, (basereg),(disp),(opc));
1394 emit_rex(1,(basereg),0,0);
1395 *(cd->mcodeptr++) = 0x81;
1396 emit_membase(cd, (basereg),(disp),(opc));
1402 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1404 emit_rex(0,(basereg),0,0);
1405 *(cd->mcodeptr++) = 0x83;
1406 emit_membase(cd, (basereg),(disp),(opc));
1409 emit_rex(0,(basereg),0,0);
1410 *(cd->mcodeptr++) = 0x81;
1411 emit_membase(cd, (basereg),(disp),(opc));
1417 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1418 emit_rex(1,(reg),0,(dreg));
1419 *(cd->mcodeptr++) = 0x85;
1420 emit_reg((reg),(dreg));
1424 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1425 emit_rex(0,(reg),0,(dreg));
1426 *(cd->mcodeptr++) = 0x85;
1427 emit_reg((reg),(dreg));
1431 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1432 *(cd->mcodeptr++) = 0xf7;
1438 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1439 *(cd->mcodeptr++) = 0x66;
1440 *(cd->mcodeptr++) = 0xf7;
1446 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1447 *(cd->mcodeptr++) = 0xf6;
1453 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1454 emit_rex(1,(reg),0,(basereg));
1455 *(cd->mcodeptr++) = 0x8d;
1456 emit_membase(cd, (basereg),(disp),(reg));
1460 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1461 emit_rex(0,(reg),0,(basereg));
1462 *(cd->mcodeptr++) = 0x8d;
1463 emit_membase(cd, (basereg),(disp),(reg));
1468 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1470 emit_rex(0,0,0,(basereg));
1471 *(cd->mcodeptr++) = 0xff;
1472 emit_membase(cd, (basereg),(disp),0);
1477 void emit_cltd(codegendata *cd) {
1478 *(cd->mcodeptr++) = 0x99;
1482 void emit_cqto(codegendata *cd) {
1484 *(cd->mcodeptr++) = 0x99;
1489 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1490 emit_rex(1,(dreg),0,(reg));
1491 *(cd->mcodeptr++) = 0x0f;
1492 *(cd->mcodeptr++) = 0xaf;
1493 emit_reg((dreg),(reg));
1497 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1498 emit_rex(0,(dreg),0,(reg));
1499 *(cd->mcodeptr++) = 0x0f;
1500 *(cd->mcodeptr++) = 0xaf;
1501 emit_reg((dreg),(reg));
1505 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1506 emit_rex(1,(dreg),0,(basereg));
1507 *(cd->mcodeptr++) = 0x0f;
1508 *(cd->mcodeptr++) = 0xaf;
1509 emit_membase(cd, (basereg),(disp),(dreg));
1513 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1514 emit_rex(0,(dreg),0,(basereg));
1515 *(cd->mcodeptr++) = 0x0f;
1516 *(cd->mcodeptr++) = 0xaf;
1517 emit_membase(cd, (basereg),(disp),(dreg));
1521 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1522 if (IS_IMM8((imm))) {
1523 emit_rex(1,0,0,(dreg));
1524 *(cd->mcodeptr++) = 0x6b;
1528 emit_rex(1,0,0,(dreg));
1529 *(cd->mcodeptr++) = 0x69;
1536 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1537 if (IS_IMM8((imm))) {
1538 emit_rex(1,(dreg),0,(reg));
1539 *(cd->mcodeptr++) = 0x6b;
1540 emit_reg((dreg),(reg));
1543 emit_rex(1,(dreg),0,(reg));
1544 *(cd->mcodeptr++) = 0x69;
1545 emit_reg((dreg),(reg));
1551 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1552 if (IS_IMM8((imm))) {
1553 emit_rex(0,(dreg),0,(reg));
1554 *(cd->mcodeptr++) = 0x6b;
1555 emit_reg((dreg),(reg));
1558 emit_rex(0,(dreg),0,(reg));
1559 *(cd->mcodeptr++) = 0x69;
1560 emit_reg((dreg),(reg));
1566 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1567 if (IS_IMM8((imm))) {
1568 emit_rex(1,(dreg),0,(basereg));
1569 *(cd->mcodeptr++) = 0x6b;
1570 emit_membase(cd, (basereg),(disp),(dreg));
1573 emit_rex(1,(dreg),0,(basereg));
1574 *(cd->mcodeptr++) = 0x69;
1575 emit_membase(cd, (basereg),(disp),(dreg));
1581 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1582 if (IS_IMM8((imm))) {
1583 emit_rex(0,(dreg),0,(basereg));
1584 *(cd->mcodeptr++) = 0x6b;
1585 emit_membase(cd, (basereg),(disp),(dreg));
1588 emit_rex(0,(dreg),0,(basereg));
1589 *(cd->mcodeptr++) = 0x69;
1590 emit_membase(cd, (basereg),(disp),(dreg));
1596 void emit_idiv_reg(codegendata *cd, s8 reg) {
1597 emit_rex(1,0,0,(reg));
1598 *(cd->mcodeptr++) = 0xf7;
1603 void emit_idivl_reg(codegendata *cd, s8 reg) {
1604 emit_rex(0,0,0,(reg));
1605 *(cd->mcodeptr++) = 0xf7;
1614 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1615 emit_rex(1,0,0,(reg));
1616 *(cd->mcodeptr++) = 0xd3;
1617 emit_reg((opc),(reg));
1621 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1622 emit_rex(0,0,0,(reg));
1623 *(cd->mcodeptr++) = 0xd3;
1624 emit_reg((opc),(reg));
1628 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1629 emit_rex(1,0,0,(basereg));
1630 *(cd->mcodeptr++) = 0xd3;
1631 emit_membase(cd, (basereg),(disp),(opc));
1635 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1636 emit_rex(0,0,0,(basereg));
1637 *(cd->mcodeptr++) = 0xd3;
1638 emit_membase(cd, (basereg),(disp),(opc));
1642 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1644 emit_rex(1,0,0,(dreg));
1645 *(cd->mcodeptr++) = 0xd1;
1646 emit_reg((opc),(dreg));
1648 emit_rex(1,0,0,(dreg));
1649 *(cd->mcodeptr++) = 0xc1;
1650 emit_reg((opc),(dreg));
1656 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1658 emit_rex(0,0,0,(dreg));
1659 *(cd->mcodeptr++) = 0xd1;
1660 emit_reg((opc),(dreg));
1662 emit_rex(0,0,0,(dreg));
1663 *(cd->mcodeptr++) = 0xc1;
1664 emit_reg((opc),(dreg));
1670 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1672 emit_rex(1,0,0,(basereg));
1673 *(cd->mcodeptr++) = 0xd1;
1674 emit_membase(cd, (basereg),(disp),(opc));
1676 emit_rex(1,0,0,(basereg));
1677 *(cd->mcodeptr++) = 0xc1;
1678 emit_membase(cd, (basereg),(disp),(opc));
1684 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1686 emit_rex(0,0,0,(basereg));
1687 *(cd->mcodeptr++) = 0xd1;
1688 emit_membase(cd, (basereg),(disp),(opc));
1690 emit_rex(0,0,0,(basereg));
1691 *(cd->mcodeptr++) = 0xc1;
1692 emit_membase(cd, (basereg),(disp),(opc));
1702 void emit_jmp_imm(codegendata *cd, s8 imm) {
1703 *(cd->mcodeptr++) = 0xe9;
1708 void emit_jmp_reg(codegendata *cd, s8 reg) {
1709 emit_rex(0,0,0,(reg));
1710 *(cd->mcodeptr++) = 0xff;
1715 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1716 *(cd->mcodeptr++) = 0x0f;
1717 *(cd->mcodeptr++) = (0x80 + (opc));
1724 * conditional set and move operations
1727 /* we need the rex byte to get all low bytes */
1728 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1730 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1731 *(cd->mcodeptr++) = 0x0f;
1732 *(cd->mcodeptr++) = (0x90 + (opc));
1737 /* we need the rex byte to get all low bytes */
1738 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1740 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1741 *(cd->mcodeptr++) = 0x0f;
1742 *(cd->mcodeptr++) = (0x90 + (opc));
1743 emit_membase(cd, (basereg),(disp),0);
1747 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1749 emit_rex(1,(dreg),0,(reg));
1750 *(cd->mcodeptr++) = 0x0f;
1751 *(cd->mcodeptr++) = (0x40 + (opc));
1752 emit_reg((dreg),(reg));
1756 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1758 emit_rex(0,(dreg),0,(reg));
1759 *(cd->mcodeptr++) = 0x0f;
1760 *(cd->mcodeptr++) = (0x40 + (opc));
1761 emit_reg((dreg),(reg));
1765 void emit_neg_reg(codegendata *cd, s8 reg)
1767 emit_rex(1,0,0,(reg));
1768 *(cd->mcodeptr++) = 0xf7;
1773 void emit_negl_reg(codegendata *cd, s8 reg)
1775 emit_rex(0,0,0,(reg));
1776 *(cd->mcodeptr++) = 0xf7;
1781 void emit_push_reg(codegendata *cd, s8 reg) {
1782 emit_rex(0,0,0,(reg));
1783 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1787 void emit_push_imm(codegendata *cd, s8 imm) {
1788 *(cd->mcodeptr++) = 0x68;
1793 void emit_pop_reg(codegendata *cd, s8 reg) {
1794 emit_rex(0,0,0,(reg));
1795 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1799 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1800 emit_rex(1,(reg),0,(dreg));
1801 *(cd->mcodeptr++) = 0x87;
1802 emit_reg((reg),(dreg));
1810 void emit_call_reg(codegendata *cd, s8 reg)
1812 emit_rex(0,0,0,(reg));
1813 *(cd->mcodeptr++) = 0xff;
1818 void emit_call_imm(codegendata *cd, s8 imm)
1820 *(cd->mcodeptr++) = 0xe8;
1825 void emit_call_mem(codegendata *cd, ptrint mem)
1827 *(cd->mcodeptr++) = 0xff;
1834 * floating point instructions (SSE2)
1836 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1837 *(cd->mcodeptr++) = 0xf2;
1838 emit_rex(0,(dreg),0,(reg));
1839 *(cd->mcodeptr++) = 0x0f;
1840 *(cd->mcodeptr++) = 0x58;
1841 emit_reg((dreg),(reg));
1845 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1846 *(cd->mcodeptr++) = 0xf3;
1847 emit_rex(0,(dreg),0,(reg));
1848 *(cd->mcodeptr++) = 0x0f;
1849 *(cd->mcodeptr++) = 0x58;
1850 emit_reg((dreg),(reg));
1854 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1855 *(cd->mcodeptr++) = 0xf3;
1856 emit_rex(1,(dreg),0,(reg));
1857 *(cd->mcodeptr++) = 0x0f;
1858 *(cd->mcodeptr++) = 0x2a;
1859 emit_reg((dreg),(reg));
1863 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1864 *(cd->mcodeptr++) = 0xf3;
1865 emit_rex(0,(dreg),0,(reg));
1866 *(cd->mcodeptr++) = 0x0f;
1867 *(cd->mcodeptr++) = 0x2a;
1868 emit_reg((dreg),(reg));
1872 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1873 *(cd->mcodeptr++) = 0xf2;
1874 emit_rex(1,(dreg),0,(reg));
1875 *(cd->mcodeptr++) = 0x0f;
1876 *(cd->mcodeptr++) = 0x2a;
1877 emit_reg((dreg),(reg));
1881 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1882 *(cd->mcodeptr++) = 0xf2;
1883 emit_rex(0,(dreg),0,(reg));
1884 *(cd->mcodeptr++) = 0x0f;
1885 *(cd->mcodeptr++) = 0x2a;
1886 emit_reg((dreg),(reg));
1890 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1891 *(cd->mcodeptr++) = 0xf3;
1892 emit_rex(0,(dreg),0,(reg));
1893 *(cd->mcodeptr++) = 0x0f;
1894 *(cd->mcodeptr++) = 0x5a;
1895 emit_reg((dreg),(reg));
1899 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1900 *(cd->mcodeptr++) = 0xf2;
1901 emit_rex(0,(dreg),0,(reg));
1902 *(cd->mcodeptr++) = 0x0f;
1903 *(cd->mcodeptr++) = 0x5a;
1904 emit_reg((dreg),(reg));
1908 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1909 *(cd->mcodeptr++) = 0xf3;
1910 emit_rex(1,(dreg),0,(reg));
1911 *(cd->mcodeptr++) = 0x0f;
1912 *(cd->mcodeptr++) = 0x2c;
1913 emit_reg((dreg),(reg));
1917 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1918 *(cd->mcodeptr++) = 0xf3;
1919 emit_rex(0,(dreg),0,(reg));
1920 *(cd->mcodeptr++) = 0x0f;
1921 *(cd->mcodeptr++) = 0x2c;
1922 emit_reg((dreg),(reg));
1926 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1927 *(cd->mcodeptr++) = 0xf2;
1928 emit_rex(1,(dreg),0,(reg));
1929 *(cd->mcodeptr++) = 0x0f;
1930 *(cd->mcodeptr++) = 0x2c;
1931 emit_reg((dreg),(reg));
1935 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1936 *(cd->mcodeptr++) = 0xf2;
1937 emit_rex(0,(dreg),0,(reg));
1938 *(cd->mcodeptr++) = 0x0f;
1939 *(cd->mcodeptr++) = 0x2c;
1940 emit_reg((dreg),(reg));
1944 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1945 *(cd->mcodeptr++) = 0xf3;
1946 emit_rex(0,(dreg),0,(reg));
1947 *(cd->mcodeptr++) = 0x0f;
1948 *(cd->mcodeptr++) = 0x5e;
1949 emit_reg((dreg),(reg));
1953 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1954 *(cd->mcodeptr++) = 0xf2;
1955 emit_rex(0,(dreg),0,(reg));
1956 *(cd->mcodeptr++) = 0x0f;
1957 *(cd->mcodeptr++) = 0x5e;
1958 emit_reg((dreg),(reg));
1962 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1963 *(cd->mcodeptr++) = 0x66;
1964 emit_rex(1,(freg),0,(reg));
1965 *(cd->mcodeptr++) = 0x0f;
1966 *(cd->mcodeptr++) = 0x6e;
1967 emit_reg((freg),(reg));
1971 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1972 *(cd->mcodeptr++) = 0x66;
1973 emit_rex(1,(freg),0,(reg));
1974 *(cd->mcodeptr++) = 0x0f;
1975 *(cd->mcodeptr++) = 0x7e;
1976 emit_reg((freg),(reg));
1980 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1981 *(cd->mcodeptr++) = 0x66;
1982 emit_rex(0,(reg),0,(basereg));
1983 *(cd->mcodeptr++) = 0x0f;
1984 *(cd->mcodeptr++) = 0x7e;
1985 emit_membase(cd, (basereg),(disp),(reg));
1989 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1990 *(cd->mcodeptr++) = 0x66;
1991 emit_rex(0,(reg),(indexreg),(basereg));
1992 *(cd->mcodeptr++) = 0x0f;
1993 *(cd->mcodeptr++) = 0x7e;
1994 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1998 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1999 *(cd->mcodeptr++) = 0x66;
2000 emit_rex(1,(dreg),0,(basereg));
2001 *(cd->mcodeptr++) = 0x0f;
2002 *(cd->mcodeptr++) = 0x6e;
2003 emit_membase(cd, (basereg),(disp),(dreg));
2007 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2008 *(cd->mcodeptr++) = 0x66;
2009 emit_rex(0,(dreg),0,(basereg));
2010 *(cd->mcodeptr++) = 0x0f;
2011 *(cd->mcodeptr++) = 0x6e;
2012 emit_membase(cd, (basereg),(disp),(dreg));
2016 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2017 *(cd->mcodeptr++) = 0x66;
2018 emit_rex(0,(dreg),(indexreg),(basereg));
2019 *(cd->mcodeptr++) = 0x0f;
2020 *(cd->mcodeptr++) = 0x6e;
2021 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2025 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2026 *(cd->mcodeptr++) = 0xf3;
2027 emit_rex(0,(dreg),0,(reg));
2028 *(cd->mcodeptr++) = 0x0f;
2029 *(cd->mcodeptr++) = 0x7e;
2030 emit_reg((dreg),(reg));
2034 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2035 *(cd->mcodeptr++) = 0x66;
2036 emit_rex(0,(reg),0,(basereg));
2037 *(cd->mcodeptr++) = 0x0f;
2038 *(cd->mcodeptr++) = 0xd6;
2039 emit_membase(cd, (basereg),(disp),(reg));
2043 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2044 *(cd->mcodeptr++) = 0xf3;
2045 emit_rex(0,(dreg),0,(basereg));
2046 *(cd->mcodeptr++) = 0x0f;
2047 *(cd->mcodeptr++) = 0x7e;
2048 emit_membase(cd, (basereg),(disp),(dreg));
2052 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2053 *(cd->mcodeptr++) = 0xf3;
2054 emit_rex(0,(reg),0,(dreg));
2055 *(cd->mcodeptr++) = 0x0f;
2056 *(cd->mcodeptr++) = 0x10;
2057 emit_reg((reg),(dreg));
2061 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2062 *(cd->mcodeptr++) = 0xf2;
2063 emit_rex(0,(reg),0,(dreg));
2064 *(cd->mcodeptr++) = 0x0f;
2065 *(cd->mcodeptr++) = 0x10;
2066 emit_reg((reg),(dreg));
2070 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2071 *(cd->mcodeptr++) = 0xf3;
2072 emit_rex(0,(reg),0,(basereg));
2073 *(cd->mcodeptr++) = 0x0f;
2074 *(cd->mcodeptr++) = 0x11;
2075 emit_membase(cd, (basereg),(disp),(reg));
2079 /* Always emit a REX byte, because the instruction size can be smaller when */
2080 /* all register indexes are smaller than 7. */
2081 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2082 *(cd->mcodeptr++) = 0xf3;
2083 emit_byte_rex((reg),0,(basereg));
2084 *(cd->mcodeptr++) = 0x0f;
2085 *(cd->mcodeptr++) = 0x11;
2086 emit_membase32(cd, (basereg),(disp),(reg));
2090 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2091 *(cd->mcodeptr++) = 0xf2;
2092 emit_rex(0,(reg),0,(basereg));
2093 *(cd->mcodeptr++) = 0x0f;
2094 *(cd->mcodeptr++) = 0x11;
2095 emit_membase(cd, (basereg),(disp),(reg));
2099 /* Always emit a REX byte, because the instruction size can be smaller when */
2100 /* all register indexes are smaller than 7. */
2101 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2102 *(cd->mcodeptr++) = 0xf2;
2103 emit_byte_rex((reg),0,(basereg));
2104 *(cd->mcodeptr++) = 0x0f;
2105 *(cd->mcodeptr++) = 0x11;
2106 emit_membase32(cd, (basereg),(disp),(reg));
2110 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2111 *(cd->mcodeptr++) = 0xf3;
2112 emit_rex(0,(dreg),0,(basereg));
2113 *(cd->mcodeptr++) = 0x0f;
2114 *(cd->mcodeptr++) = 0x10;
2115 emit_membase(cd, (basereg),(disp),(dreg));
2119 /* Always emit a REX byte, because the instruction size can be smaller when */
2120 /* all register indexes are smaller than 7. */
2121 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2122 *(cd->mcodeptr++) = 0xf3;
2123 emit_byte_rex((dreg),0,(basereg));
2124 *(cd->mcodeptr++) = 0x0f;
2125 *(cd->mcodeptr++) = 0x10;
2126 emit_membase32(cd, (basereg),(disp),(dreg));
2130 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2132 emit_rex(0,(dreg),0,(basereg));
2133 *(cd->mcodeptr++) = 0x0f;
2134 *(cd->mcodeptr++) = 0x12;
2135 emit_membase(cd, (basereg),(disp),(dreg));
2139 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2141 emit_rex(0,(reg),0,(basereg));
2142 *(cd->mcodeptr++) = 0x0f;
2143 *(cd->mcodeptr++) = 0x13;
2144 emit_membase(cd, (basereg),(disp),(reg));
2148 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2149 *(cd->mcodeptr++) = 0xf2;
2150 emit_rex(0,(dreg),0,(basereg));
2151 *(cd->mcodeptr++) = 0x0f;
2152 *(cd->mcodeptr++) = 0x10;
2153 emit_membase(cd, (basereg),(disp),(dreg));
2157 /* Always emit a REX byte, because the instruction size can be smaller when */
2158 /* all register indexes are smaller than 7. */
2159 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2160 *(cd->mcodeptr++) = 0xf2;
2161 emit_byte_rex((dreg),0,(basereg));
2162 *(cd->mcodeptr++) = 0x0f;
2163 *(cd->mcodeptr++) = 0x10;
2164 emit_membase32(cd, (basereg),(disp),(dreg));
2168 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2170 *(cd->mcodeptr++) = 0x66;
2171 emit_rex(0,(dreg),0,(basereg));
2172 *(cd->mcodeptr++) = 0x0f;
2173 *(cd->mcodeptr++) = 0x12;
2174 emit_membase(cd, (basereg),(disp),(dreg));
2178 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2180 *(cd->mcodeptr++) = 0x66;
2181 emit_rex(0,(reg),0,(basereg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x13;
2184 emit_membase(cd, (basereg),(disp),(reg));
2188 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2189 *(cd->mcodeptr++) = 0xf3;
2190 emit_rex(0,(reg),(indexreg),(basereg));
2191 *(cd->mcodeptr++) = 0x0f;
2192 *(cd->mcodeptr++) = 0x11;
2193 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2197 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2198 *(cd->mcodeptr++) = 0xf2;
2199 emit_rex(0,(reg),(indexreg),(basereg));
2200 *(cd->mcodeptr++) = 0x0f;
2201 *(cd->mcodeptr++) = 0x11;
2202 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2206 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2207 *(cd->mcodeptr++) = 0xf3;
2208 emit_rex(0,(dreg),(indexreg),(basereg));
2209 *(cd->mcodeptr++) = 0x0f;
2210 *(cd->mcodeptr++) = 0x10;
2211 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2215 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2216 *(cd->mcodeptr++) = 0xf2;
2217 emit_rex(0,(dreg),(indexreg),(basereg));
2218 *(cd->mcodeptr++) = 0x0f;
2219 *(cd->mcodeptr++) = 0x10;
2220 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2224 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2225 *(cd->mcodeptr++) = 0xf3;
2226 emit_rex(0,(dreg),0,(reg));
2227 *(cd->mcodeptr++) = 0x0f;
2228 *(cd->mcodeptr++) = 0x59;
2229 emit_reg((dreg),(reg));
2233 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2234 *(cd->mcodeptr++) = 0xf2;
2235 emit_rex(0,(dreg),0,(reg));
2236 *(cd->mcodeptr++) = 0x0f;
2237 *(cd->mcodeptr++) = 0x59;
2238 emit_reg((dreg),(reg));
2242 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2243 *(cd->mcodeptr++) = 0xf3;
2244 emit_rex(0,(dreg),0,(reg));
2245 *(cd->mcodeptr++) = 0x0f;
2246 *(cd->mcodeptr++) = 0x5c;
2247 emit_reg((dreg),(reg));
2251 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2252 *(cd->mcodeptr++) = 0xf2;
2253 emit_rex(0,(dreg),0,(reg));
2254 *(cd->mcodeptr++) = 0x0f;
2255 *(cd->mcodeptr++) = 0x5c;
2256 emit_reg((dreg),(reg));
2260 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2261 emit_rex(0,(dreg),0,(reg));
2262 *(cd->mcodeptr++) = 0x0f;
2263 *(cd->mcodeptr++) = 0x2e;
2264 emit_reg((dreg),(reg));
2268 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2269 *(cd->mcodeptr++) = 0x66;
2270 emit_rex(0,(dreg),0,(reg));
2271 *(cd->mcodeptr++) = 0x0f;
2272 *(cd->mcodeptr++) = 0x2e;
2273 emit_reg((dreg),(reg));
2277 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2278 emit_rex(0,(dreg),0,(reg));
2279 *(cd->mcodeptr++) = 0x0f;
2280 *(cd->mcodeptr++) = 0x57;
2281 emit_reg((dreg),(reg));
2285 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2286 emit_rex(0,(dreg),0,(basereg));
2287 *(cd->mcodeptr++) = 0x0f;
2288 *(cd->mcodeptr++) = 0x57;
2289 emit_membase(cd, (basereg),(disp),(dreg));
2293 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2294 *(cd->mcodeptr++) = 0x66;
2295 emit_rex(0,(dreg),0,(reg));
2296 *(cd->mcodeptr++) = 0x0f;
2297 *(cd->mcodeptr++) = 0x57;
2298 emit_reg((dreg),(reg));
2302 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2303 *(cd->mcodeptr++) = 0x66;
2304 emit_rex(0,(dreg),0,(basereg));
2305 *(cd->mcodeptr++) = 0x0f;
2306 *(cd->mcodeptr++) = 0x57;
2307 emit_membase(cd, (basereg),(disp),(dreg));
2311 /* system instructions ********************************************************/
2313 void emit_rdtsc(codegendata *cd)
2315 *(cd->mcodeptr++) = 0x0f;
2316 *(cd->mcodeptr++) = 0x31;
2321 * These are local overrides for various environment variables in Emacs.
2322 * Please do not remove this and leave it at the end of the file, where
2323 * Emacs will automagically detect them.
2324 * ---------------------------------------------------------------------
2327 * indent-tabs-mode: t