1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8211 2007-07-18 19:52:23Z michi $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #include "threads/lock-common.h"
44 #include "vm/builtin.h"
45 #include "vm/exceptions.h"
47 #include "vm/jit/abi.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
55 #include "vmcore/options.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff;
81 M_ILD(tempreg, REG_SP, disp);
85 M_LLD(tempreg, REG_SP, disp);
88 M_FLD(tempreg, REG_SP, disp);
91 M_DLD(tempreg, REG_SP, disp);
94 vm_abort("emit_load: unknown type %d", src->type);
100 reg = src->vv.regoff;
106 /* emit_store ******************************************************************
108 This function generates the code to store the result of an
109 operation back into a spilled pseudo-variable. If the
110 pseudo-variable has not been spilled in the first place, this
111 function will generate nothing.
113 *******************************************************************************/
115 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
124 /* get required compiler data */
129 /* do we have to generate a conditional move? */
131 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
132 /* the passed register d is actually the source register */
136 /* Only pass the opcode to codegen_reg_of_var to get the real
137 destination register. */
139 opcode = iptr->opc & ICMD_OPCODE_MASK;
141 /* get the real destination register */
143 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
145 /* and emit the conditional move */
147 emit_cmovxx(cd, iptr, s, d);
151 if (IS_INMEMORY(dst->flags)) {
154 disp = dst->vv.regoff;
160 M_LST(d, REG_SP, disp);
163 M_FST(d, REG_SP, disp);
166 M_DST(d, REG_SP, disp);
169 vm_abort("emit_store: unknown type %d", dst->type);
175 /* emit_copy *******************************************************************
177 Generates a register/memory to register/memory copy.
179 *******************************************************************************/
181 void emit_copy(jitdata *jd, instruction *iptr)
188 /* get required compiler data */
192 /* get source and destination variables */
194 src = VAROP(iptr->s1);
195 dst = VAROP(iptr->dst);
197 if ((src->vv.regoff != dst->vv.regoff) ||
198 ((src->flags ^ dst->flags) & INMEMORY)) {
200 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
201 /* emit nothing, as the value won't be used anyway */
205 /* If one of the variables resides in memory, we can eliminate
206 the register move from/to the temporary register with the
207 order of getting the destination register and the load. */
209 if (IS_INMEMORY(src->flags)) {
210 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
211 s1 = emit_load(jd, iptr, src, d);
214 s1 = emit_load(jd, iptr, src, REG_IFTMP);
215 d = codegen_reg_of_var(iptr->opc, dst, s1);
230 vm_abort("emit_copy: unknown type %d", src->type);
234 emit_store(jd, iptr, dst, d);
239 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
242 switch (iptr->flags.fields.condition) {
266 /* emit_branch *****************************************************************
268 Emits the code for conditional and unconditional branchs.
270 *******************************************************************************/
272 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
276 /* NOTE: A displacement overflow cannot happen. */
278 /* check which branch to generate */
280 if (condition == BRANCH_UNCONDITIONAL) {
282 /* calculate the different displacements */
284 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
286 M_JMP_IMM(branchdisp);
289 /* calculate the different displacements */
291 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
325 vm_abort("emit_branch: unknown condition %d", condition);
331 /* emit_arithmetic_check *******************************************************
333 Emit an ArithmeticException check.
335 *******************************************************************************/
337 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
339 if (INSTRUCTION_MUST_CHECK(iptr)) {
342 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
347 /* emit_arrayindexoutofbounds_check ********************************************
349 Emit a ArrayIndexOutOfBoundsException check.
351 *******************************************************************************/
353 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
355 if (INSTRUCTION_MUST_CHECK(iptr)) {
356 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
357 M_ICMP(REG_ITMP3, s2);
359 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
364 /* emit_classcast_check ********************************************************
366 Emit a ClassCastException check.
368 *******************************************************************************/
370 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
372 if (INSTRUCTION_MUST_CHECK(iptr)) {
384 vm_abort("emit_classcast_check: unknown condition %d", condition);
386 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
391 /* emit_nullpointer_check ******************************************************
393 Emit a NullPointerException check.
395 *******************************************************************************/
397 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
399 if (INSTRUCTION_MUST_CHECK(iptr)) {
402 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
407 /* emit_exception_check ********************************************************
409 Emit an Exception check.
411 *******************************************************************************/
413 void emit_exception_check(codegendata *cd, instruction *iptr)
415 if (INSTRUCTION_MUST_CHECK(iptr)) {
418 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
423 /* emit_patcher_stubs **********************************************************
425 Generates the code for the patcher stubs.
427 *******************************************************************************/
429 void emit_patcher_stubs(jitdata *jd)
439 /* get required compiler data */
443 /* generate code patching stub call code */
447 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
448 /* check size of code segment */
452 /* Get machine code which is patched back in later. A
453 `call rel32' is 5 bytes long (but read 8 bytes). */
455 savedmcodeptr = cd->mcodebase + pref->branchpos;
456 mcode = *((u8 *) savedmcodeptr);
458 /* patch in `call rel32' to call the following code */
460 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
461 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
463 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
465 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
467 /* move pointer to java_objectheader onto stack */
469 #if defined(ENABLE_THREADS)
470 /* create a virtual java_objectheader */
472 (void) dseg_add_unique_address(cd, NULL); /* flcword */
473 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
474 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
476 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
482 /* move machine code bytes and classinfo pointer into registers */
484 M_MOV_IMM(mcode, REG_ITMP3);
487 M_MOV_IMM(pref->ref, REG_ITMP3);
490 M_MOV_IMM(pref->disp, REG_ITMP3);
493 M_MOV_IMM(pref->patcher, REG_ITMP3);
496 if (targetdisp == 0) {
497 targetdisp = cd->mcodeptr - cd->mcodebase;
499 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
503 M_JMP_IMM((cd->mcodebase + targetdisp) -
504 (cd->mcodeptr + PATCHER_CALL_SIZE));
510 /* emit_verbosecall_enter ******************************************************
512 Generates the code for the call trace.
514 *******************************************************************************/
517 void emit_verbosecall_enter(jitdata *jd)
525 /* get required compiler data */
533 /* mark trace code */
537 /* additional +1 is for 16-byte stack alignment */
539 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
541 /* save argument registers */
543 for (i = 0; i < INT_ARG_CNT; i++)
544 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
546 for (i = 0; i < FLT_ARG_CNT; i++)
547 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
549 /* save temporary registers for leaf methods */
551 if (jd->isleafmethod) {
552 for (i = 0; i < INT_TMP_CNT; i++)
553 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
555 for (i = 0; i < FLT_TMP_CNT; i++)
556 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
559 /* show integer hex code for float arguments */
561 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
562 /* If the paramtype is a float, we have to right shift all
563 following integer registers. */
565 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
566 for (k = INT_ARG_CNT - 2; k >= i; k--)
567 M_MOV(abi_registers_integer_argument[k],
568 abi_registers_integer_argument[k + 1]);
570 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
571 abi_registers_integer_argument[i]);
576 M_MOV_IMM(m, REG_ITMP2);
577 M_AST(REG_ITMP2, REG_SP, 0 * 8);
578 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
581 /* restore argument registers */
583 for (i = 0; i < INT_ARG_CNT; i++)
584 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
586 for (i = 0; i < FLT_ARG_CNT; i++)
587 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
589 /* restore temporary registers for leaf methods */
591 if (jd->isleafmethod) {
592 for (i = 0; i < INT_TMP_CNT; i++)
593 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
595 for (i = 0; i < FLT_TMP_CNT; i++)
596 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
599 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
601 /* mark trace code */
605 #endif /* !defined(NDEBUG) */
608 /* emit_verbosecall_exit *******************************************************
610 Generates the code for the call trace.
612 *******************************************************************************/
615 void emit_verbosecall_exit(jitdata *jd)
621 /* get required compiler data */
627 /* mark trace code */
631 M_ASUB_IMM(2 * 8, REG_SP);
633 M_LST(REG_RESULT, REG_SP, 0 * 8);
634 M_DST(REG_FRESULT, REG_SP, 1 * 8);
636 M_INTMOVE(REG_RESULT, REG_A0);
637 M_FLTMOVE(REG_FRESULT, REG_FA0);
638 M_FLTMOVE(REG_FRESULT, REG_FA1);
639 M_MOV_IMM(m, REG_A1);
641 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
644 M_LLD(REG_RESULT, REG_SP, 0 * 8);
645 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
647 M_AADD_IMM(2 * 8, REG_SP);
649 /* mark trace code */
653 #endif /* !defined(NDEBUG) */
656 /* code generation functions **************************************************/
658 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
660 if ((basereg == REG_SP) || (basereg == R12)) {
662 emit_address_byte(0, dreg, REG_SP);
663 emit_address_byte(0, REG_SP, REG_SP);
665 } else if (IS_IMM8(disp)) {
666 emit_address_byte(1, dreg, REG_SP);
667 emit_address_byte(0, REG_SP, REG_SP);
671 emit_address_byte(2, dreg, REG_SP);
672 emit_address_byte(0, REG_SP, REG_SP);
676 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
677 emit_address_byte(0,(dreg),(basereg));
679 } else if ((basereg) == RIP) {
680 emit_address_byte(0, dreg, RBP);
685 emit_address_byte(1, dreg, basereg);
689 emit_address_byte(2, dreg, basereg);
696 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
698 if ((basereg == REG_SP) || (basereg == R12)) {
699 emit_address_byte(2, dreg, REG_SP);
700 emit_address_byte(0, REG_SP, REG_SP);
704 emit_address_byte(2, dreg, basereg);
710 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
713 emit_address_byte(0, reg, 4);
714 emit_address_byte(scale, indexreg, 5);
717 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
718 emit_address_byte(0, reg, 4);
719 emit_address_byte(scale, indexreg, basereg);
721 else if (IS_IMM8(disp)) {
722 emit_address_byte(1, reg, 4);
723 emit_address_byte(scale, indexreg, basereg);
727 emit_address_byte(2, reg, 4);
728 emit_address_byte(scale, indexreg, basereg);
734 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
737 varinfo *v_s1,*v_s2,*v_dst;
740 /* get required compiler data */
744 v_s1 = VAROP(iptr->s1);
745 v_s2 = VAROP(iptr->sx.s23.s2);
746 v_dst = VAROP(iptr->dst);
748 s1 = v_s1->vv.regoff;
749 s2 = v_s2->vv.regoff;
750 d = v_dst->vv.regoff;
752 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
754 if (IS_INMEMORY(v_dst->flags)) {
755 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
757 M_ILD(RCX, REG_SP, s2);
758 emit_shiftl_membase(cd, shift_op, REG_SP, d);
761 M_ILD(RCX, REG_SP, s2);
762 M_ILD(REG_ITMP2, REG_SP, s1);
763 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
764 M_IST(REG_ITMP2, REG_SP, d);
767 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
768 /* s1 may be equal to RCX */
771 M_ILD(REG_ITMP1, REG_SP, s2);
772 M_IST(s1, REG_SP, d);
773 M_INTMOVE(REG_ITMP1, RCX);
776 M_IST(s1, REG_SP, d);
777 M_ILD(RCX, REG_SP, s2);
781 M_ILD(RCX, REG_SP, s2);
782 M_IST(s1, REG_SP, d);
785 emit_shiftl_membase(cd, shift_op, REG_SP, d);
787 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
790 emit_shiftl_membase(cd, shift_op, REG_SP, d);
794 M_ILD(REG_ITMP2, REG_SP, s1);
795 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
796 M_IST(REG_ITMP2, REG_SP, d);
800 /* s1 may be equal to RCX */
801 M_IST(s1, REG_SP, d);
803 emit_shiftl_membase(cd, shift_op, REG_SP, d);
806 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
814 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
815 M_ILD(RCX, REG_SP, s2);
816 M_ILD(d, REG_SP, s1);
817 emit_shiftl_reg(cd, shift_op, d);
819 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
820 /* s1 may be equal to RCX */
822 M_ILD(RCX, REG_SP, s2);
823 emit_shiftl_reg(cd, shift_op, d);
825 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
827 M_ILD(d, REG_SP, s1);
828 emit_shiftl_reg(cd, shift_op, d);
831 /* s1 may be equal to RCX */
834 /* d cannot be used to backup s1 since this would
836 M_INTMOVE(s1, REG_ITMP3);
838 M_INTMOVE(REG_ITMP3, d);
846 /* d may be equal to s2 */
850 emit_shiftl_reg(cd, shift_op, d);
854 M_INTMOVE(REG_ITMP3, RCX);
856 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
861 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
864 varinfo *v_s1,*v_s2,*v_dst;
867 /* get required compiler data */
871 v_s1 = VAROP(iptr->s1);
872 v_s2 = VAROP(iptr->sx.s23.s2);
873 v_dst = VAROP(iptr->dst);
875 s1 = v_s1->vv.regoff;
876 s2 = v_s2->vv.regoff;
877 d = v_dst->vv.regoff;
879 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
881 if (IS_INMEMORY(v_dst->flags)) {
882 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
884 M_ILD(RCX, REG_SP, s2);
885 emit_shift_membase(cd, shift_op, REG_SP, d);
888 M_ILD(RCX, REG_SP, s2);
889 M_LLD(REG_ITMP2, REG_SP, s1);
890 emit_shift_reg(cd, shift_op, REG_ITMP2);
891 M_LST(REG_ITMP2, REG_SP, d);
894 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
895 /* s1 may be equal to RCX */
898 M_ILD(REG_ITMP1, REG_SP, s2);
899 M_LST(s1, REG_SP, d);
900 M_INTMOVE(REG_ITMP1, RCX);
903 M_LST(s1, REG_SP, d);
904 M_ILD(RCX, REG_SP, s2);
908 M_ILD(RCX, REG_SP, s2);
909 M_LST(s1, REG_SP, d);
912 emit_shift_membase(cd, shift_op, REG_SP, d);
914 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
917 emit_shift_membase(cd, shift_op, REG_SP, d);
921 M_LLD(REG_ITMP2, REG_SP, s1);
922 emit_shift_reg(cd, shift_op, REG_ITMP2);
923 M_LST(REG_ITMP2, REG_SP, d);
927 /* s1 may be equal to RCX */
928 M_LST(s1, REG_SP, d);
930 emit_shift_membase(cd, shift_op, REG_SP, d);
933 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
941 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
942 M_ILD(RCX, REG_SP, s2);
943 M_LLD(d, REG_SP, s1);
944 emit_shift_reg(cd, shift_op, d);
946 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
947 /* s1 may be equal to RCX */
949 M_ILD(RCX, REG_SP, s2);
950 emit_shift_reg(cd, shift_op, d);
952 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
954 M_LLD(d, REG_SP, s1);
955 emit_shift_reg(cd, shift_op, d);
958 /* s1 may be equal to RCX */
961 /* d cannot be used to backup s1 since this would
963 M_INTMOVE(s1, REG_ITMP3);
965 M_INTMOVE(REG_ITMP3, d);
973 /* d may be equal to s2 */
977 emit_shift_reg(cd, shift_op, d);
981 M_INTMOVE(REG_ITMP3, RCX);
983 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
988 /* low-level code emitter functions *******************************************/
990 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
992 emit_rex(1,(reg),0,(dreg));
993 *(cd->mcodeptr++) = 0x89;
994 emit_reg((reg),(dreg));
998 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1000 emit_rex(1,0,0,(reg));
1001 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1006 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1008 emit_rex(0,(reg),0,(dreg));
1009 *(cd->mcodeptr++) = 0x89;
1010 emit_reg((reg),(dreg));
1014 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1015 emit_rex(0,0,0,(reg));
1016 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1021 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1022 emit_rex(1,(reg),0,(basereg));
1023 *(cd->mcodeptr++) = 0x8b;
1024 emit_membase(cd, (basereg),(disp),(reg));
1029 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1030 * constant membase immediate length of 32bit
1032 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1033 emit_rex(1,(reg),0,(basereg));
1034 *(cd->mcodeptr++) = 0x8b;
1035 emit_membase32(cd, (basereg),(disp),(reg));
1039 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1041 emit_rex(0,(reg),0,(basereg));
1042 *(cd->mcodeptr++) = 0x8b;
1043 emit_membase(cd, (basereg),(disp),(reg));
1047 /* ATTENTION: Always emit a REX byte, because the instruction size can
1048 be smaller when all register indexes are smaller than 7. */
1049 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1051 emit_byte_rex((reg),0,(basereg));
1052 *(cd->mcodeptr++) = 0x8b;
1053 emit_membase32(cd, (basereg),(disp),(reg));
1057 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1058 emit_rex(1,(reg),0,(basereg));
1059 *(cd->mcodeptr++) = 0x89;
1060 emit_membase(cd, (basereg),(disp),(reg));
1064 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1065 emit_rex(1,(reg),0,(basereg));
1066 *(cd->mcodeptr++) = 0x89;
1067 emit_membase32(cd, (basereg),(disp),(reg));
1071 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1072 emit_rex(0,(reg),0,(basereg));
1073 *(cd->mcodeptr++) = 0x89;
1074 emit_membase(cd, (basereg),(disp),(reg));
1078 /* Always emit a REX byte, because the instruction size can be smaller when */
1079 /* all register indexes are smaller than 7. */
1080 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1081 emit_byte_rex((reg),0,(basereg));
1082 *(cd->mcodeptr++) = 0x89;
1083 emit_membase32(cd, (basereg),(disp),(reg));
1087 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1088 emit_rex(1,(reg),(indexreg),(basereg));
1089 *(cd->mcodeptr++) = 0x8b;
1090 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1094 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1095 emit_rex(0,(reg),(indexreg),(basereg));
1096 *(cd->mcodeptr++) = 0x8b;
1097 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1101 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1102 emit_rex(1,(reg),(indexreg),(basereg));
1103 *(cd->mcodeptr++) = 0x89;
1104 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1108 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1109 emit_rex(0,(reg),(indexreg),(basereg));
1110 *(cd->mcodeptr++) = 0x89;
1111 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1115 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1116 *(cd->mcodeptr++) = 0x66;
1117 emit_rex(0,(reg),(indexreg),(basereg));
1118 *(cd->mcodeptr++) = 0x89;
1119 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1123 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1124 emit_byte_rex((reg),(indexreg),(basereg));
1125 *(cd->mcodeptr++) = 0x88;
1126 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1130 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1131 emit_rex(1,0,0,(basereg));
1132 *(cd->mcodeptr++) = 0xc7;
1133 emit_membase(cd, (basereg),(disp),0);
1138 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1139 emit_rex(1,0,0,(basereg));
1140 *(cd->mcodeptr++) = 0xc7;
1141 emit_membase32(cd, (basereg),(disp),0);
1146 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1147 emit_rex(0,0,0,(basereg));
1148 *(cd->mcodeptr++) = 0xc7;
1149 emit_membase(cd, (basereg),(disp),0);
1154 /* Always emit a REX byte, because the instruction size can be smaller when */
1155 /* all register indexes are smaller than 7. */
1156 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1157 emit_byte_rex(0,0,(basereg));
1158 *(cd->mcodeptr++) = 0xc7;
1159 emit_membase32(cd, (basereg),(disp),0);
1164 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1166 emit_rex(1,(dreg),0,(reg));
1167 *(cd->mcodeptr++) = 0x0f;
1168 *(cd->mcodeptr++) = 0xbe;
1169 /* XXX: why do reg and dreg have to be exchanged */
1170 emit_reg((dreg),(reg));
1174 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1176 emit_rex(1,(dreg),0,(reg));
1177 *(cd->mcodeptr++) = 0x0f;
1178 *(cd->mcodeptr++) = 0xbf;
1179 /* XXX: why do reg and dreg have to be exchanged */
1180 emit_reg((dreg),(reg));
1184 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1186 emit_rex(1,(dreg),0,(reg));
1187 *(cd->mcodeptr++) = 0x63;
1188 /* XXX: why do reg and dreg have to be exchanged */
1189 emit_reg((dreg),(reg));
1193 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1195 emit_rex(1,(dreg),0,(reg));
1196 *(cd->mcodeptr++) = 0x0f;
1197 *(cd->mcodeptr++) = 0xb7;
1198 /* XXX: why do reg and dreg have to be exchanged */
1199 emit_reg((dreg),(reg));
1203 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1204 emit_rex(1,(reg),(indexreg),(basereg));
1205 *(cd->mcodeptr++) = 0x0f;
1206 *(cd->mcodeptr++) = 0xbf;
1207 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1211 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1212 emit_rex(1,(reg),(indexreg),(basereg));
1213 *(cd->mcodeptr++) = 0x0f;
1214 *(cd->mcodeptr++) = 0xbe;
1215 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1219 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1220 emit_rex(1,(reg),(indexreg),(basereg));
1221 *(cd->mcodeptr++) = 0x0f;
1222 *(cd->mcodeptr++) = 0xb7;
1223 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1227 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1229 emit_rex(1,0,(indexreg),(basereg));
1230 *(cd->mcodeptr++) = 0xc7;
1231 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1236 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1238 emit_rex(0,0,(indexreg),(basereg));
1239 *(cd->mcodeptr++) = 0xc7;
1240 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1245 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1247 *(cd->mcodeptr++) = 0x66;
1248 emit_rex(0,0,(indexreg),(basereg));
1249 *(cd->mcodeptr++) = 0xc7;
1250 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1255 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1257 emit_rex(0,0,(indexreg),(basereg));
1258 *(cd->mcodeptr++) = 0xc6;
1259 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1264 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1266 emit_rex(1, dreg, 0, 0);
1267 *(cd->mcodeptr++) = 0x8b;
1268 emit_address_byte(0, dreg, 4);
1276 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1278 emit_rex(1,(reg),0,(dreg));
1279 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1280 emit_reg((reg),(dreg));
1284 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1286 emit_rex(0,(reg),0,(dreg));
1287 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1288 emit_reg((reg),(dreg));
1292 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1294 emit_rex(1,(reg),0,(basereg));
1295 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1296 emit_membase(cd, (basereg),(disp),(reg));
1300 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1302 emit_rex(0,(reg),0,(basereg));
1303 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1304 emit_membase(cd, (basereg),(disp),(reg));
1308 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1310 emit_rex(1,(reg),0,(basereg));
1311 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1312 emit_membase(cd, (basereg),(disp),(reg));
1316 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1318 emit_rex(0,(reg),0,(basereg));
1319 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1320 emit_membase(cd, (basereg),(disp),(reg));
1324 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1326 emit_rex(1,0,0,(dreg));
1327 *(cd->mcodeptr++) = 0x83;
1328 emit_reg((opc),(dreg));
1331 emit_rex(1,0,0,(dreg));
1332 *(cd->mcodeptr++) = 0x81;
1333 emit_reg((opc),(dreg));
1339 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1341 emit_rex(1,0,0,(dreg));
1342 *(cd->mcodeptr++) = 0x81;
1343 emit_reg((opc),(dreg));
1348 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1350 emit_rex(0,0,0,(dreg));
1351 *(cd->mcodeptr++) = 0x81;
1352 emit_reg((opc),(dreg));
1357 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1359 emit_rex(0,0,0,(dreg));
1360 *(cd->mcodeptr++) = 0x83;
1361 emit_reg((opc),(dreg));
1364 emit_rex(0,0,0,(dreg));
1365 *(cd->mcodeptr++) = 0x81;
1366 emit_reg((opc),(dreg));
1372 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1374 emit_rex(1,(basereg),0,0);
1375 *(cd->mcodeptr++) = 0x83;
1376 emit_membase(cd, (basereg),(disp),(opc));
1379 emit_rex(1,(basereg),0,0);
1380 *(cd->mcodeptr++) = 0x81;
1381 emit_membase(cd, (basereg),(disp),(opc));
1387 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1389 emit_rex(0,(basereg),0,0);
1390 *(cd->mcodeptr++) = 0x83;
1391 emit_membase(cd, (basereg),(disp),(opc));
1394 emit_rex(0,(basereg),0,0);
1395 *(cd->mcodeptr++) = 0x81;
1396 emit_membase(cd, (basereg),(disp),(opc));
1402 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1403 emit_rex(1,(reg),0,(dreg));
1404 *(cd->mcodeptr++) = 0x85;
1405 emit_reg((reg),(dreg));
1409 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1410 emit_rex(0,(reg),0,(dreg));
1411 *(cd->mcodeptr++) = 0x85;
1412 emit_reg((reg),(dreg));
1416 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1417 *(cd->mcodeptr++) = 0xf7;
1423 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1424 *(cd->mcodeptr++) = 0x66;
1425 *(cd->mcodeptr++) = 0xf7;
1431 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1432 *(cd->mcodeptr++) = 0xf6;
1438 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1439 emit_rex(1,(reg),0,(basereg));
1440 *(cd->mcodeptr++) = 0x8d;
1441 emit_membase(cd, (basereg),(disp),(reg));
1445 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1446 emit_rex(0,(reg),0,(basereg));
1447 *(cd->mcodeptr++) = 0x8d;
1448 emit_membase(cd, (basereg),(disp),(reg));
1453 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1455 emit_rex(0,0,0,(basereg));
1456 *(cd->mcodeptr++) = 0xff;
1457 emit_membase(cd, (basereg),(disp),0);
1462 void emit_cltd(codegendata *cd) {
1463 *(cd->mcodeptr++) = 0x99;
1467 void emit_cqto(codegendata *cd) {
1469 *(cd->mcodeptr++) = 0x99;
1474 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1475 emit_rex(1,(dreg),0,(reg));
1476 *(cd->mcodeptr++) = 0x0f;
1477 *(cd->mcodeptr++) = 0xaf;
1478 emit_reg((dreg),(reg));
1482 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1483 emit_rex(0,(dreg),0,(reg));
1484 *(cd->mcodeptr++) = 0x0f;
1485 *(cd->mcodeptr++) = 0xaf;
1486 emit_reg((dreg),(reg));
1490 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1491 emit_rex(1,(dreg),0,(basereg));
1492 *(cd->mcodeptr++) = 0x0f;
1493 *(cd->mcodeptr++) = 0xaf;
1494 emit_membase(cd, (basereg),(disp),(dreg));
1498 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1499 emit_rex(0,(dreg),0,(basereg));
1500 *(cd->mcodeptr++) = 0x0f;
1501 *(cd->mcodeptr++) = 0xaf;
1502 emit_membase(cd, (basereg),(disp),(dreg));
1506 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1507 if (IS_IMM8((imm))) {
1508 emit_rex(1,0,0,(dreg));
1509 *(cd->mcodeptr++) = 0x6b;
1513 emit_rex(1,0,0,(dreg));
1514 *(cd->mcodeptr++) = 0x69;
1521 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1522 if (IS_IMM8((imm))) {
1523 emit_rex(1,(dreg),0,(reg));
1524 *(cd->mcodeptr++) = 0x6b;
1525 emit_reg((dreg),(reg));
1528 emit_rex(1,(dreg),0,(reg));
1529 *(cd->mcodeptr++) = 0x69;
1530 emit_reg((dreg),(reg));
1536 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1537 if (IS_IMM8((imm))) {
1538 emit_rex(0,(dreg),0,(reg));
1539 *(cd->mcodeptr++) = 0x6b;
1540 emit_reg((dreg),(reg));
1543 emit_rex(0,(dreg),0,(reg));
1544 *(cd->mcodeptr++) = 0x69;
1545 emit_reg((dreg),(reg));
1551 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1552 if (IS_IMM8((imm))) {
1553 emit_rex(1,(dreg),0,(basereg));
1554 *(cd->mcodeptr++) = 0x6b;
1555 emit_membase(cd, (basereg),(disp),(dreg));
1558 emit_rex(1,(dreg),0,(basereg));
1559 *(cd->mcodeptr++) = 0x69;
1560 emit_membase(cd, (basereg),(disp),(dreg));
1566 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1567 if (IS_IMM8((imm))) {
1568 emit_rex(0,(dreg),0,(basereg));
1569 *(cd->mcodeptr++) = 0x6b;
1570 emit_membase(cd, (basereg),(disp),(dreg));
1573 emit_rex(0,(dreg),0,(basereg));
1574 *(cd->mcodeptr++) = 0x69;
1575 emit_membase(cd, (basereg),(disp),(dreg));
1581 void emit_idiv_reg(codegendata *cd, s8 reg) {
1582 emit_rex(1,0,0,(reg));
1583 *(cd->mcodeptr++) = 0xf7;
1588 void emit_idivl_reg(codegendata *cd, s8 reg) {
1589 emit_rex(0,0,0,(reg));
1590 *(cd->mcodeptr++) = 0xf7;
1596 void emit_ret(codegendata *cd) {
1597 *(cd->mcodeptr++) = 0xc3;
1605 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1606 emit_rex(1,0,0,(reg));
1607 *(cd->mcodeptr++) = 0xd3;
1608 emit_reg((opc),(reg));
1612 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1613 emit_rex(0,0,0,(reg));
1614 *(cd->mcodeptr++) = 0xd3;
1615 emit_reg((opc),(reg));
1619 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1620 emit_rex(1,0,0,(basereg));
1621 *(cd->mcodeptr++) = 0xd3;
1622 emit_membase(cd, (basereg),(disp),(opc));
1626 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1627 emit_rex(0,0,0,(basereg));
1628 *(cd->mcodeptr++) = 0xd3;
1629 emit_membase(cd, (basereg),(disp),(opc));
1633 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1635 emit_rex(1,0,0,(dreg));
1636 *(cd->mcodeptr++) = 0xd1;
1637 emit_reg((opc),(dreg));
1639 emit_rex(1,0,0,(dreg));
1640 *(cd->mcodeptr++) = 0xc1;
1641 emit_reg((opc),(dreg));
1647 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1649 emit_rex(0,0,0,(dreg));
1650 *(cd->mcodeptr++) = 0xd1;
1651 emit_reg((opc),(dreg));
1653 emit_rex(0,0,0,(dreg));
1654 *(cd->mcodeptr++) = 0xc1;
1655 emit_reg((opc),(dreg));
1661 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1663 emit_rex(1,0,0,(basereg));
1664 *(cd->mcodeptr++) = 0xd1;
1665 emit_membase(cd, (basereg),(disp),(opc));
1667 emit_rex(1,0,0,(basereg));
1668 *(cd->mcodeptr++) = 0xc1;
1669 emit_membase(cd, (basereg),(disp),(opc));
1675 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1677 emit_rex(0,0,0,(basereg));
1678 *(cd->mcodeptr++) = 0xd1;
1679 emit_membase(cd, (basereg),(disp),(opc));
1681 emit_rex(0,0,0,(basereg));
1682 *(cd->mcodeptr++) = 0xc1;
1683 emit_membase(cd, (basereg),(disp),(opc));
1693 void emit_jmp_imm(codegendata *cd, s8 imm) {
1694 *(cd->mcodeptr++) = 0xe9;
1699 void emit_jmp_reg(codegendata *cd, s8 reg) {
1700 emit_rex(0,0,0,(reg));
1701 *(cd->mcodeptr++) = 0xff;
1706 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1707 *(cd->mcodeptr++) = 0x0f;
1708 *(cd->mcodeptr++) = (0x80 + (opc));
1715 * conditional set and move operations
1718 /* we need the rex byte to get all low bytes */
1719 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1721 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1722 *(cd->mcodeptr++) = 0x0f;
1723 *(cd->mcodeptr++) = (0x90 + (opc));
1728 /* we need the rex byte to get all low bytes */
1729 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1731 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1732 *(cd->mcodeptr++) = 0x0f;
1733 *(cd->mcodeptr++) = (0x90 + (opc));
1734 emit_membase(cd, (basereg),(disp),0);
1738 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1740 emit_rex(1,(dreg),0,(reg));
1741 *(cd->mcodeptr++) = 0x0f;
1742 *(cd->mcodeptr++) = (0x40 + (opc));
1743 emit_reg((dreg),(reg));
1747 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1749 emit_rex(0,(dreg),0,(reg));
1750 *(cd->mcodeptr++) = 0x0f;
1751 *(cd->mcodeptr++) = (0x40 + (opc));
1752 emit_reg((dreg),(reg));
1756 void emit_neg_reg(codegendata *cd, s8 reg)
1758 emit_rex(1,0,0,(reg));
1759 *(cd->mcodeptr++) = 0xf7;
1764 void emit_negl_reg(codegendata *cd, s8 reg)
1766 emit_rex(0,0,0,(reg));
1767 *(cd->mcodeptr++) = 0xf7;
1772 void emit_push_reg(codegendata *cd, s8 reg) {
1773 emit_rex(0,0,0,(reg));
1774 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1778 void emit_push_imm(codegendata *cd, s8 imm) {
1779 *(cd->mcodeptr++) = 0x68;
1784 void emit_pop_reg(codegendata *cd, s8 reg) {
1785 emit_rex(0,0,0,(reg));
1786 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1790 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1791 emit_rex(1,(reg),0,(dreg));
1792 *(cd->mcodeptr++) = 0x87;
1793 emit_reg((reg),(dreg));
1797 void emit_nop(codegendata *cd) {
1798 *(cd->mcodeptr++) = 0x90;
1806 void emit_call_reg(codegendata *cd, s8 reg)
1808 emit_rex(0,0,0,(reg));
1809 *(cd->mcodeptr++) = 0xff;
1814 void emit_call_imm(codegendata *cd, s8 imm)
1816 *(cd->mcodeptr++) = 0xe8;
1821 void emit_call_mem(codegendata *cd, ptrint mem)
1823 *(cd->mcodeptr++) = 0xff;
1830 * floating point instructions (SSE2)
1832 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1833 *(cd->mcodeptr++) = 0xf2;
1834 emit_rex(0,(dreg),0,(reg));
1835 *(cd->mcodeptr++) = 0x0f;
1836 *(cd->mcodeptr++) = 0x58;
1837 emit_reg((dreg),(reg));
1841 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1842 *(cd->mcodeptr++) = 0xf3;
1843 emit_rex(0,(dreg),0,(reg));
1844 *(cd->mcodeptr++) = 0x0f;
1845 *(cd->mcodeptr++) = 0x58;
1846 emit_reg((dreg),(reg));
1850 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1851 *(cd->mcodeptr++) = 0xf3;
1852 emit_rex(1,(dreg),0,(reg));
1853 *(cd->mcodeptr++) = 0x0f;
1854 *(cd->mcodeptr++) = 0x2a;
1855 emit_reg((dreg),(reg));
1859 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1860 *(cd->mcodeptr++) = 0xf3;
1861 emit_rex(0,(dreg),0,(reg));
1862 *(cd->mcodeptr++) = 0x0f;
1863 *(cd->mcodeptr++) = 0x2a;
1864 emit_reg((dreg),(reg));
1868 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1869 *(cd->mcodeptr++) = 0xf2;
1870 emit_rex(1,(dreg),0,(reg));
1871 *(cd->mcodeptr++) = 0x0f;
1872 *(cd->mcodeptr++) = 0x2a;
1873 emit_reg((dreg),(reg));
1877 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1878 *(cd->mcodeptr++) = 0xf2;
1879 emit_rex(0,(dreg),0,(reg));
1880 *(cd->mcodeptr++) = 0x0f;
1881 *(cd->mcodeptr++) = 0x2a;
1882 emit_reg((dreg),(reg));
1886 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1887 *(cd->mcodeptr++) = 0xf3;
1888 emit_rex(0,(dreg),0,(reg));
1889 *(cd->mcodeptr++) = 0x0f;
1890 *(cd->mcodeptr++) = 0x5a;
1891 emit_reg((dreg),(reg));
1895 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1896 *(cd->mcodeptr++) = 0xf2;
1897 emit_rex(0,(dreg),0,(reg));
1898 *(cd->mcodeptr++) = 0x0f;
1899 *(cd->mcodeptr++) = 0x5a;
1900 emit_reg((dreg),(reg));
1904 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1905 *(cd->mcodeptr++) = 0xf3;
1906 emit_rex(1,(dreg),0,(reg));
1907 *(cd->mcodeptr++) = 0x0f;
1908 *(cd->mcodeptr++) = 0x2c;
1909 emit_reg((dreg),(reg));
1913 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1914 *(cd->mcodeptr++) = 0xf3;
1915 emit_rex(0,(dreg),0,(reg));
1916 *(cd->mcodeptr++) = 0x0f;
1917 *(cd->mcodeptr++) = 0x2c;
1918 emit_reg((dreg),(reg));
1922 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1923 *(cd->mcodeptr++) = 0xf2;
1924 emit_rex(1,(dreg),0,(reg));
1925 *(cd->mcodeptr++) = 0x0f;
1926 *(cd->mcodeptr++) = 0x2c;
1927 emit_reg((dreg),(reg));
1931 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1932 *(cd->mcodeptr++) = 0xf2;
1933 emit_rex(0,(dreg),0,(reg));
1934 *(cd->mcodeptr++) = 0x0f;
1935 *(cd->mcodeptr++) = 0x2c;
1936 emit_reg((dreg),(reg));
1940 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1941 *(cd->mcodeptr++) = 0xf3;
1942 emit_rex(0,(dreg),0,(reg));
1943 *(cd->mcodeptr++) = 0x0f;
1944 *(cd->mcodeptr++) = 0x5e;
1945 emit_reg((dreg),(reg));
1949 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1950 *(cd->mcodeptr++) = 0xf2;
1951 emit_rex(0,(dreg),0,(reg));
1952 *(cd->mcodeptr++) = 0x0f;
1953 *(cd->mcodeptr++) = 0x5e;
1954 emit_reg((dreg),(reg));
1958 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1959 *(cd->mcodeptr++) = 0x66;
1960 emit_rex(1,(freg),0,(reg));
1961 *(cd->mcodeptr++) = 0x0f;
1962 *(cd->mcodeptr++) = 0x6e;
1963 emit_reg((freg),(reg));
1967 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1968 *(cd->mcodeptr++) = 0x66;
1969 emit_rex(1,(freg),0,(reg));
1970 *(cd->mcodeptr++) = 0x0f;
1971 *(cd->mcodeptr++) = 0x7e;
1972 emit_reg((freg),(reg));
1976 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1977 *(cd->mcodeptr++) = 0x66;
1978 emit_rex(0,(reg),0,(basereg));
1979 *(cd->mcodeptr++) = 0x0f;
1980 *(cd->mcodeptr++) = 0x7e;
1981 emit_membase(cd, (basereg),(disp),(reg));
1985 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1986 *(cd->mcodeptr++) = 0x66;
1987 emit_rex(0,(reg),(indexreg),(basereg));
1988 *(cd->mcodeptr++) = 0x0f;
1989 *(cd->mcodeptr++) = 0x7e;
1990 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1994 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1995 *(cd->mcodeptr++) = 0x66;
1996 emit_rex(1,(dreg),0,(basereg));
1997 *(cd->mcodeptr++) = 0x0f;
1998 *(cd->mcodeptr++) = 0x6e;
1999 emit_membase(cd, (basereg),(disp),(dreg));
2003 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2004 *(cd->mcodeptr++) = 0x66;
2005 emit_rex(0,(dreg),0,(basereg));
2006 *(cd->mcodeptr++) = 0x0f;
2007 *(cd->mcodeptr++) = 0x6e;
2008 emit_membase(cd, (basereg),(disp),(dreg));
2012 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2013 *(cd->mcodeptr++) = 0x66;
2014 emit_rex(0,(dreg),(indexreg),(basereg));
2015 *(cd->mcodeptr++) = 0x0f;
2016 *(cd->mcodeptr++) = 0x6e;
2017 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2021 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2022 *(cd->mcodeptr++) = 0xf3;
2023 emit_rex(0,(dreg),0,(reg));
2024 *(cd->mcodeptr++) = 0x0f;
2025 *(cd->mcodeptr++) = 0x7e;
2026 emit_reg((dreg),(reg));
2030 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2031 *(cd->mcodeptr++) = 0x66;
2032 emit_rex(0,(reg),0,(basereg));
2033 *(cd->mcodeptr++) = 0x0f;
2034 *(cd->mcodeptr++) = 0xd6;
2035 emit_membase(cd, (basereg),(disp),(reg));
2039 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2040 *(cd->mcodeptr++) = 0xf3;
2041 emit_rex(0,(dreg),0,(basereg));
2042 *(cd->mcodeptr++) = 0x0f;
2043 *(cd->mcodeptr++) = 0x7e;
2044 emit_membase(cd, (basereg),(disp),(dreg));
2048 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2049 *(cd->mcodeptr++) = 0xf3;
2050 emit_rex(0,(reg),0,(dreg));
2051 *(cd->mcodeptr++) = 0x0f;
2052 *(cd->mcodeptr++) = 0x10;
2053 emit_reg((reg),(dreg));
2057 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2058 *(cd->mcodeptr++) = 0xf2;
2059 emit_rex(0,(reg),0,(dreg));
2060 *(cd->mcodeptr++) = 0x0f;
2061 *(cd->mcodeptr++) = 0x10;
2062 emit_reg((reg),(dreg));
2066 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2067 *(cd->mcodeptr++) = 0xf3;
2068 emit_rex(0,(reg),0,(basereg));
2069 *(cd->mcodeptr++) = 0x0f;
2070 *(cd->mcodeptr++) = 0x11;
2071 emit_membase(cd, (basereg),(disp),(reg));
2075 /* Always emit a REX byte, because the instruction size can be smaller when */
2076 /* all register indexes are smaller than 7. */
2077 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2078 *(cd->mcodeptr++) = 0xf3;
2079 emit_byte_rex((reg),0,(basereg));
2080 *(cd->mcodeptr++) = 0x0f;
2081 *(cd->mcodeptr++) = 0x11;
2082 emit_membase32(cd, (basereg),(disp),(reg));
2086 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2087 *(cd->mcodeptr++) = 0xf2;
2088 emit_rex(0,(reg),0,(basereg));
2089 *(cd->mcodeptr++) = 0x0f;
2090 *(cd->mcodeptr++) = 0x11;
2091 emit_membase(cd, (basereg),(disp),(reg));
2095 /* Always emit a REX byte, because the instruction size can be smaller when */
2096 /* all register indexes are smaller than 7. */
2097 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2098 *(cd->mcodeptr++) = 0xf2;
2099 emit_byte_rex((reg),0,(basereg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x11;
2102 emit_membase32(cd, (basereg),(disp),(reg));
2106 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2107 *(cd->mcodeptr++) = 0xf3;
2108 emit_rex(0,(dreg),0,(basereg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x10;
2111 emit_membase(cd, (basereg),(disp),(dreg));
2115 /* Always emit a REX byte, because the instruction size can be smaller when */
2116 /* all register indexes are smaller than 7. */
2117 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2118 *(cd->mcodeptr++) = 0xf3;
2119 emit_byte_rex((dreg),0,(basereg));
2120 *(cd->mcodeptr++) = 0x0f;
2121 *(cd->mcodeptr++) = 0x10;
2122 emit_membase32(cd, (basereg),(disp),(dreg));
2126 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2128 emit_rex(0,(dreg),0,(basereg));
2129 *(cd->mcodeptr++) = 0x0f;
2130 *(cd->mcodeptr++) = 0x12;
2131 emit_membase(cd, (basereg),(disp),(dreg));
2135 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2137 emit_rex(0,(reg),0,(basereg));
2138 *(cd->mcodeptr++) = 0x0f;
2139 *(cd->mcodeptr++) = 0x13;
2140 emit_membase(cd, (basereg),(disp),(reg));
2144 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2145 *(cd->mcodeptr++) = 0xf2;
2146 emit_rex(0,(dreg),0,(basereg));
2147 *(cd->mcodeptr++) = 0x0f;
2148 *(cd->mcodeptr++) = 0x10;
2149 emit_membase(cd, (basereg),(disp),(dreg));
2153 /* Always emit a REX byte, because the instruction size can be smaller when */
2154 /* all register indexes are smaller than 7. */
2155 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2156 *(cd->mcodeptr++) = 0xf2;
2157 emit_byte_rex((dreg),0,(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x10;
2160 emit_membase32(cd, (basereg),(disp),(dreg));
2164 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2166 *(cd->mcodeptr++) = 0x66;
2167 emit_rex(0,(dreg),0,(basereg));
2168 *(cd->mcodeptr++) = 0x0f;
2169 *(cd->mcodeptr++) = 0x12;
2170 emit_membase(cd, (basereg),(disp),(dreg));
2174 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2176 *(cd->mcodeptr++) = 0x66;
2177 emit_rex(0,(reg),0,(basereg));
2178 *(cd->mcodeptr++) = 0x0f;
2179 *(cd->mcodeptr++) = 0x13;
2180 emit_membase(cd, (basereg),(disp),(reg));
2184 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2185 *(cd->mcodeptr++) = 0xf3;
2186 emit_rex(0,(reg),(indexreg),(basereg));
2187 *(cd->mcodeptr++) = 0x0f;
2188 *(cd->mcodeptr++) = 0x11;
2189 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2193 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2194 *(cd->mcodeptr++) = 0xf2;
2195 emit_rex(0,(reg),(indexreg),(basereg));
2196 *(cd->mcodeptr++) = 0x0f;
2197 *(cd->mcodeptr++) = 0x11;
2198 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2202 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2203 *(cd->mcodeptr++) = 0xf3;
2204 emit_rex(0,(dreg),(indexreg),(basereg));
2205 *(cd->mcodeptr++) = 0x0f;
2206 *(cd->mcodeptr++) = 0x10;
2207 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2211 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2212 *(cd->mcodeptr++) = 0xf2;
2213 emit_rex(0,(dreg),(indexreg),(basereg));
2214 *(cd->mcodeptr++) = 0x0f;
2215 *(cd->mcodeptr++) = 0x10;
2216 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2220 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2221 *(cd->mcodeptr++) = 0xf3;
2222 emit_rex(0,(dreg),0,(reg));
2223 *(cd->mcodeptr++) = 0x0f;
2224 *(cd->mcodeptr++) = 0x59;
2225 emit_reg((dreg),(reg));
2229 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2230 *(cd->mcodeptr++) = 0xf2;
2231 emit_rex(0,(dreg),0,(reg));
2232 *(cd->mcodeptr++) = 0x0f;
2233 *(cd->mcodeptr++) = 0x59;
2234 emit_reg((dreg),(reg));
2238 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2239 *(cd->mcodeptr++) = 0xf3;
2240 emit_rex(0,(dreg),0,(reg));
2241 *(cd->mcodeptr++) = 0x0f;
2242 *(cd->mcodeptr++) = 0x5c;
2243 emit_reg((dreg),(reg));
2247 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2248 *(cd->mcodeptr++) = 0xf2;
2249 emit_rex(0,(dreg),0,(reg));
2250 *(cd->mcodeptr++) = 0x0f;
2251 *(cd->mcodeptr++) = 0x5c;
2252 emit_reg((dreg),(reg));
2256 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2257 emit_rex(0,(dreg),0,(reg));
2258 *(cd->mcodeptr++) = 0x0f;
2259 *(cd->mcodeptr++) = 0x2e;
2260 emit_reg((dreg),(reg));
2264 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2265 *(cd->mcodeptr++) = 0x66;
2266 emit_rex(0,(dreg),0,(reg));
2267 *(cd->mcodeptr++) = 0x0f;
2268 *(cd->mcodeptr++) = 0x2e;
2269 emit_reg((dreg),(reg));
2273 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2274 emit_rex(0,(dreg),0,(reg));
2275 *(cd->mcodeptr++) = 0x0f;
2276 *(cd->mcodeptr++) = 0x57;
2277 emit_reg((dreg),(reg));
2281 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2282 emit_rex(0,(dreg),0,(basereg));
2283 *(cd->mcodeptr++) = 0x0f;
2284 *(cd->mcodeptr++) = 0x57;
2285 emit_membase(cd, (basereg),(disp),(dreg));
2289 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2290 *(cd->mcodeptr++) = 0x66;
2291 emit_rex(0,(dreg),0,(reg));
2292 *(cd->mcodeptr++) = 0x0f;
2293 *(cd->mcodeptr++) = 0x57;
2294 emit_reg((dreg),(reg));
2298 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2299 *(cd->mcodeptr++) = 0x66;
2300 emit_rex(0,(dreg),0,(basereg));
2301 *(cd->mcodeptr++) = 0x0f;
2302 *(cd->mcodeptr++) = 0x57;
2303 emit_membase(cd, (basereg),(disp),(dreg));
2307 /* system instructions ********************************************************/
2309 void emit_rdtsc(codegendata *cd)
2311 *(cd->mcodeptr++) = 0x0f;
2312 *(cd->mcodeptr++) = 0x31;
2317 * These are local overrides for various environment variables in Emacs.
2318 * Please do not remove this and leave it at the end of the file, where
2319 * Emacs will automagically detect them.
2320 * ---------------------------------------------------------------------
2323 * indent-tabs-mode: t